High-performance RISC-DSP

Abstract

A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seamless transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low overhead interrupts.

1 . A digital signal processor, comprising: 
 a first execution pipeline and a second execution pipeline capable of executing instructions;    instruction fetch logic that simultaneously fetches two instructions and routes them to the first execution pipeline and the second execution pipeline; and    control logic to allow values from the first execution pipeline to be bypassed to the second execution pipeline,    wherein the first execution pipeline is configured to execute a multiply-accumulate instruction.    
     
     
         2 . The digital signal processor of  claim 1 , wherein the instruction fetch logic includes logic that fetches dual SIMD instructions.  
     
     
         3 . The digital signal processor of  claim 1 , further including a first register and a second register, wherein the instruction fetch logic fetches a first portion of a word into the first register and simultaneously fetches a second portion of the word into the second register.  
     
     
         4 . The digital signal processor of  claim 1 , further including an eight port general register file.  
     
     
         5 . The digital signal processor of  claim 4 , wherein the general register file includes 
 four read ports, and    four write ports.    
     
     
         6 - 10 . (canceled)  
     
     
         11 . The digital signal processor of  claim 1 , further comprising: 
 a register that is configured to store at least one mode value that determines how the multiply-accumulate instruction is executed.    
     
     
         12 . The digital signal processor of  claim 11 , wherein the at least one mode value is one of a truncate mode value, a saturation mode value and a fractional mode value.  
     
     
         13 . A method for processing instructions in a digital signal processor, comprising: 
 (1) simultaneously fetching a first instruction and a second instruction;    (2) routing the first instruction to a first execution pipeline and the second instruction to a second execution pipeline; and    (3) executing the first instruction and the second instruction, 
 wherein, if the first instruction is a multiply-accumulate instruction, the first instruction is executed in accordance with at least one mode value stored in a register, the at least one mode value being one of a truncate mode value, a saturation mode value and a fractional mode value.  
   
     
     
         14 . The method of  claim 13 , wherein (1) comprises simultaneously fetching SIMD instructions.  
     
     
         15 . The method of  claim 13 , further comprising: 
 simultaneously fetching a first portion of a word into a first register and a second portion of the word into a second register.    
     
     
         16 . A system for processing instructions, comprising: 
 a processor that includes 
 a first execution pipeline and a second execution pipeline capable of executing instructions,  
 instruction fetch logic that simultaneously fetches two instructions and routes them to the first execution pipeline and the second execution pipeline, and  
 control logic to allow values from the first execution pipeline to be bypassed to the second execution pipeline,  
 wherein the first execution pipeline is configured to execute a multiply-accumulate instruction; and  
   a memory coupled to the processor.    
     
     
         17 . The system of  claim 16 , wherein the instruction fetch logic includes logic that fetches SIMD instructions.  
     
     
         18 . The system of  claim 16 , further including a first register and a second register, wherein the instruction fetch logic fetches a first portion of a word into the first register and simultaneously fetches a second portion of the word into the second register.  
     
     
         19 . The system of  claim 16 , further including an eight port general register file.  
     
     
         20 . The system of  claim 19 , wherein the general register file includes 
 four read ports, and    four write ports.    
     
     
         21 . The system of  claim 16 , further comprising: 
 a register that is configured to store at least one mode value that determines how the multiply-accumulate instruction is executed.    
     
     
         22 . The digital signal processor of  claim 21 , wherein the at least one mode value is one of a truncate mode value, a saturation mode value and a fractional mode value.