Electrostatic (ESD) protection circuit for an integrated circuit

Abstract

An output stage protection system for protecting NMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an embodiment, the output stage includes a pair of relatively low voltage NMOS devices coupled to a current source and IC core outputs. A first pair of relatively high voltage NMOS devices is coupled to the relatively low voltage pair and a biasing circuit. A second pair of relatively high voltage NMOS devices is coupled to a resistor, the first pair, and first and second output nodes, respectively. One or more diodes are coupled in series between the first and second output nodes and the resistor. In an embodiment, the output stage protection system protects NMOS devices in the output stage from electrostatic discharge (ESD). Input/output (I/O) pad ESD protection circuits are coupled to the I/O pads and include a clamp coupled to a local net.

1  . An electrostatic discharge (ESD) protection apparatus for an I/O pad, comprising: 
 a local net, wherein the local net includes an ESD voltage based upon an ESD event on the I/O pad; and    an ESD clamp coupled to the I/O pad to discharge the ESD voltage to a ground, wherein a supply voltage of the ESD clamp is based upon the ESD voltage.    
   
   
       2 . The ESD protection apparatus of  claim 1 , wherein the ESD clamp further comprises: 
 an inverter, wherein a supply voltage of the inverter is based upon the ESD voltage;    a low pass filter coupled between the local net and an input of the inverter; and    a switch coupled between the local net and the ground, wherein the switch discharges the ESD voltage to the ground based upon an output of the low pass filter.    
   
   
       4 . The ESD protection apparatus of claim  3 , wherein the switch comprises a transistor having a gate coupled to an output of the inverter, a drain coupled to the local net, and a source coupled to the ground.  
   
   
       5 . The ESD protection apparatus of claim  3 , wherein the low pass filter further includes: 
 a first resistor coupled between the input of the inverter and the local net; and    a capacitor coupled between the input of the inverter and the ground.    
   
   
       6 . The ESD protection apparatus of  claim 1 , further comprising: 
 a first group of one or more diodes coupled between the I/O pad and the local net.    
   
   
       7 . The ESD protection apparatus of  claim 6 , wherein the ESD event forward biases the first group of one or more diodes.  
   
   
       8 . The ESD protection apparatus of  claim 4 , further comprising: a second resistor coupled between the ground and the local net.  
   
   
       9 . The ESD protection apparatus of  claim 8 , wherein the second resistor substantially ensures that the ESD voltage is substantially less than a voltage rating of the transistor.  
   
   
       10 . The ESD protection apparatus of  claim 1 , further comprising: 
 a second group of one or more diodes coupled between the I/O pad and the ground.    
   
   
       11 . An electrostatic discharge (ESD) protection apparatus for an I/O pad, comprising: 
 a group of one or more diodes coupled to the I/O pad;    a low pass filter coupled to the group of one or more diodes;    an inverter coupled to an output of the low pass filter; and    a switch coupled to the inverter, wherein the switch discharges an ESD voltage to a ground based upon an output of the low pass filter.    
   
   
       12 . The ESD protection apparatus of  claim 11 , wherein an ESD event on the I/O pad forward biases the group of one or more diodes.  
   
   
       13 . The ESD protection apparatus of  claim 11 , wherein the switch comprises a transistor having a gate coupled to an output of the inverter, a drain coupled to the group of one ore more diodes, and a source coupled to the ground.  
   
   
       14 . The ESD protection apparatus of  claim 13 , wherein the transistor discharges the ESD voltage to the ground based upon the output of the low pass filter.  
   
   
       15 . The ESD protection apparatus of  claim 11 , wherein the low pass filter further includes: 
 a first resistor coupled between an input of the inverter and the group of one ore more diodes; and    a capacitor coupled between the input of the inverter and the ground.    
   
   
       16 . The ESD protection apparatus of  claim 13 , further comprising: a second resistor coupled between the ground and the group of one ore more diodes.  
   
   
       17 . The ESD protection apparatus of  claim 17 , wherein the second resistor substantially ensures that the ESD voltage is substantially less than a voltage rating of the transistor.