Substrate-biased Silicon Diode for Electrostatic Discharge Protection

Abstract

An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions.

1 . An integrated circuit device receiving signals from a signal pad, comprising at least one substrate-biased silicon diode responsive to the signals from the signal pad for providing electrostatic discharge protection.  
   
   
       2 . The integrated circuit device as claimed in  claim 1 , further comprising a detection circuit for detecting the signals from the signal pad and providing a bias voltage to the at least one substrate-biased silicon diode.  
   
   
       3 . The integrated circuit device as claimed in  claim 2 , wherein the detection circuit includes a first transistor, a second transistor, and a resistor-capacitor circuit, and wherein a gate of the first transistor is coupled to a gate of the-second transistor and the resistor-capacitor circuit.  
   
   
       4 . The integrated circuit device as claimed in  claim 3 , wherein a drain of the first transistor and a drain of the second transistor are coupled to a substrate of the at least one substrate-biased silicon diode to provide a bias voltage.  
   
   
       5 . The integrated circuit device as claimed in  claim 3 , wherein a source of the first transistor is coupled to a VDD signal and a source of the second transistor is coupled to a V SS  signal.  
   
   
       6 . The integrated circuit device as claimed in  claim 2 , wherein the detection circuit comprises a resistor-capacitor circuit having a delay constant longer than the duration of the signals from the signal pad.  
   
   
       7 . The integrated circuit device as claimed in  claim 2 , wherein the detection circuit comprises a resistor-capacitor circuit coupled in parallel to a transistor network.  
   
   
       8 . The integrated circuit device claimed in  claim 1 , wherein the at least one substrate-biased silicon diode includes one or more serially coupled substrate-biased silicon diodes.  
   
   
       9 . The integrated circuit device as claimed in  claim 1 , wherein the at least one substrate-biased silicon diode includes a p-type polysilicon portion, an n-type polysilicon portion and a center polysilicon portion disposed between and contiguous with the p-type and n-type polysilicon portions.  
   
   
       10 . The integrated circuit device as claimed in  claim 1 , wherein the at least one substrate-biased silicon diode includes a p-portion and an n-portion, and wherein the signal pad is coupled to the p-portion of the at least one substrate-biased silicon diode.  
   
   
       11 . The integrated circuit device as claimed in  claim 1 , wherein the signals from the signal pad are electrostatic pulses.  
   
   
       12 . An integrated circuit device receiving signals from a signal pad, comprising: a first plurality of serially coupled substrate-biased silicon diodes responsive to the signals from the signal pad for providing electrostatic discharge protection from the signals, each of the first plurality of substrate-biased silicon diodes including a p-portion and an n-portion; a second plurality of serially coupled substrate-biased silicon diodes responsive to the signals from the signal pad for providing electrostatic discharge protection from the signals, each of the second plurality of substrate-biased silicon diodes including a p-portion and an n-portion; and a detection circuit for detecting signals from the signal pad and providing a bias voltage to the first and second plurality of substrate-biased silicon diodes, wherein the signal pad is coupled to the p-portion of one of the first plurality of substrate-biased silicon diodes and the n-portion of one of the second plurality of the substrate-biased silicon diodes.  
   
   
       13 . The integrated circuit device as claimed in  claim 12 , wherein the detection circuit comprises a first transistor; a second transistor, and a resistor-capacitor network, and wherein a gate of the first transistor is coupled to a gate of the second transistor and the resistor-capacitor circuit.  
   
   
       14 . The integrated circuit device as claimed in  claim 13 , wherein a drain of the first transistor and a drain of the second transistor are coupled to a substrate of the first and second plurality of substrate-biased silicon diodes to provide a bias voltage to the first and second plurality of substrate-biased silicon diodes.