Programmable pipeline fabric having mechanism to terminate signal propagation

Abstract

A method and apparatus for storing and using “register use” information to determine when a register is being used for the last time so that power savings may be achieved is disclosed. The register use information may take the form of “last read” information for a particular register. The last read information may be used to force the value of the register, after being read, to zero or to clock only that register while masking off the other registers. Several methods and hardware variations are disclosed for using the register use information to achieve power savings.

1 .- 16 . (canceled)  
     
     
         17 . A power saving method, comprising: 
 providing configuration information to each of a plurality of series connected pass register files, each pass register file comprised of a plurality of registers;    providing clock pulses to each of said pass register files;    determining for each pass register file, if the registers within said pass register file should be clocked with said clock pulses based on a read address, a write address, and a last read data for said pass register file; and    selectively applying said clock pulses to the registers within each of said pass register files based on said determining.    
     
     
         18 . The method of  claim 17  wherein said determining is performed one of remotely or locally with respect to each of said pass register files.  
     
     
         19 . The method of  claim 17  wherein said determining is additionally based on a state of a preceding pass register file in said plurality of series connected pass register files.  
     
     
         20 . The method of  claim 19  wherein said determining is performed by a state machine.  
     
     
         21 . The method of  claim 17  wherein said determining is performed by a plurality of mask units each positioned locally with respect to one of said pass register files, and wherein said selectively applying is performed by a plurality of logic gates, each responsive to one of said plurality of mask units and each receiving said clock pulses.  
     
     
         22 . A power saving circuit for use in a reconfigurable apparatus of the type constructed of a plurality of serially connected pass register files, each pass register file constructed of a plurality of registers, said power saving circuit comprising: 
 a plurality of mask units, each producing a signal for controlling the application of clock pulses to one of said pass register files based on a read address, a write address, and a last read data for said pass register file; and    a plurality of logic gates, each responsive to one of said mask units for selectively applying clock pulses to the registers within one of said pass register files.    
     
     
         23 . The circuit of  claim 22  wherein each of said mask units is located one of remotely or locally with respect to each of said pass register files.  
     
     
         24 . The circuit of  claim 22  wherein each of said mask units is additionally responsive to a state of a mask unit for a preceding pass register file in said plurality of series connected pass register files.  
     
     
         25 . The circuit of  claim 22  wherein each of said mask units includes a state machine.  
     
     
         26 . The circuit of  claim 22  wherein said plurality of logic gates includes a plurality of AND gates.  
     
     
         27 . A reconfigurable apparatus, comprising: 
 a plurality of series connected pass register files each comprised of a plurality of registers, each of said pass register files adapted to receive configuration information;    a plurality of mask units, each producing a signal for controlling the application of clock pulses to one of said pass register files based on a read address, a write address, and a last read data for said pass register file; and    a plurality of logic gates, each responsive to one of said mask units for selectively applying clock pulses to the registers within one of said pass register files.    
     
     
         28 . The apparatus of  claim 27  wherein each of said mask units is located one of remotely or locally with respect to each of said pass register files.  
     
     
         29 . The apparatus of  claim 27  wherein each of said mask units is additionally responsive to a state of a mask unit for a preceding pass register file in said plurality of series connected pass register files.  
     
     
         30 . The apparatus of  claim 27  wherein each of said mask units includes a state machine.  
     
     
         31 . The apparatus of  claim 27  wherein said plurality of logic gates includes a plurality of AND gates.