Semiconductor device having capacitor formed in multilayer wiring structure

Abstract

A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.

1 . A semiconductor device comprising: 
 a multilayer wiring structure including a plurality of wiring layers formed on a substrate;    a capacitor arranged in a first wiring layer in the multilayer wiring structure and including a lower electrode, a dielectric film, and an upper electrode;    a first via formed in the first wiring layer and connected directly to a top surface of the upper electrode of the capacitor; and    a second via formed in an overlying wiring layer stacked on the first wiring layer, the second via being connected directly on the first via and the second via being connected to a wiring formed in the overlying wiring layer,    wherein the first via is formed to have a larger cross section than that of the second via.    
   
   
       2 . (canceled)  
   
   
       3 . A semiconductor device according to  claim 1 , wherein the predetermined wiring layer has a third via formed on the lower electrode and a wiring connected to the third via and buried in a surface of the predetermined wiring layer.  
   
   
       4 . (canceled)  
   
   
       5 . A semiconductor device according to  claim 3 , wherein the wiring comprises copper, and a copper diffusion stopper film is formed on the surface of the first wiring layer to prevent diffusion of the copper forming the wiring.  
   
   
       6 . (canceled)  
   
   
       7 . A semiconductor device according to  claim 1 , wherein the overlying wiring layer has a wiring connected to a top of the second via and buried in a surface of the overlying wiring layer.  
   
   
       8 - 9 . (canceled)  
   
   
       10 . A semiconductor device according to  claim 1 , wherein a third via formed above the lower electrode of the capacitor is provided in the first wiring layer; 
 a fourth via connected on the third via and formed to be thinner than the third via is provided in the overlying wiring layer; and    the second and fourth vias are connected to the first and second wirings, respectively, buried in a surface of the overlying wiring layer.    
   
   
       11 . A semiconductor device according to  claim 1 , wherein the lower electrode of the capacitor is connected to a wiring buried in a surface of an underlying wiring layer formed under the predetermined wiring layer in which the capacitor is formed.  
   
   
       12 - 13 . (canceled)