Interconnect structure having a silicide/germanide cap layer

Abstract

An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.

1 . An interconnect structure of an integrated circuit, the interconnect structure comprising:
 a semiconductor substrate;   a low-k dielectric layer over the semiconductor substrate;   a conductor in the low-k dielectric layer; and   a cap layer on the conductor, wherein the cap layer has at least a top portion comprising a metal silicide/germanide.   
   
   
       2 . The interconnect structure of  claim 1 , wherein the cap layer is fully silicided or germanided. 
   
   
       3 . The interconnect structure of  claim 1 , wherein only the top portion of the cap layer is silicided or germanided. 
   
   
       4 . The interconnect structure of  claim 1 , wherein the cap layer comprises a material selected from the group consisting essentially of silicon, germanium, cobalt, nickel, tungsten, molybdenum, tantalum, boron, iron, phosphorus, and combinations thereof. 
   
   
       5 . The interconnect structure of  claim 1 , wherein the top portion of the cap layer comprises silicide only. 
   
   
       6 . The interconnect structure of  claim 1 , wherein the top portion of the cap layer comprises germanide only. 
   
   
       7 . The interconnect structure of  claim 1 , wherein the top portion of the cap layer comprises germano-silicide. 
   
   
       8 . The interconnect structure of  claim 1  further comprising a via over the cap layer, wherein the via and the cap layer are electrically coupled. 
   
   
       9 . The interconnect structure of  claim 1  further comprising:
 a dielectric layer over at least portions of the low-k dielectric layer and the cap layer, wherein the dielectric layer has a dielectric constant of greater than about 3.5, and comprises a material selected from the group consisting essentially of SiN, SiC, SiCN, SiCO, carbon-based materials, CH x , CO y H x , and combinations thereof; and   an additional low-k dielectric layer over the dielectric layer.   
   
   
       10 . The interconnect structure of  claim 1 , wherein the low-k dielectric layer has a k value of less than about 3.5. 
   
   
       11 . The interconnect structure of  claim 1 , wherein the conductor comprises copper. 
   
   
       12 . A damascene structure comprising:
 a first low-k dielectric layer;   an opening in the first low-k dielectric layer, wherein the opening extends from a top surface to a bottom surface of the first low-k dielectric layer;   a first copper feature filled in the opening; and   a metallic cap layer on the first copper feature, wherein the metallic cap layer comprises silicide/germanide.   
   
   
       13 . The damascene structure of  claim 12  further comprising:
 a second dielectric layer overlying the low-k first dielectric layer;   a via structure in the second dielectric layer, wherein a bottom surface of the via structure is in contact with the metallic cap layer; and   a second copper feature in the via structure and in the second dielectric layer.   
   
   
       14 . The damascene structure of  claim 13  further comprising an additional metallic cap layer on the second copper feature, wherein the additional metallic cap layer comprises silicide/germanide. 
   
   
       15 . The damascene structure of  claim 12 , wherein the first copper feature comprises a copper via and a copper line on the copper via. 
   
   
       16 . The damascene structure of  claim 12 , wherein only a top portion of the metallic cap layer is silicided/germanided. 
   
   
       17 . The damascene structure of  claim 12 , wherein the metallic cap layer is fully silicided/germanided. 
   
   
       18 . A semiconductor structure comprising:
 a semiconductor substrate;   a low-k dielectric layer over the semiconductor substrate;   a conductor in the low-k dielectric layer;   a cap layer on the conductor, wherein the cap layer has at least a top portion comprising a metal silicide/germanide; and   an etch stop layer over the low-k dielectric layer.   
   
   
       19 . The semiconductor structure of  claim 18 , wherein the etch stop layer extends on the cap layer. 
   
   
       20 . The semiconductor structure of  claim 18  further comprising a chemical mechanical polish (CMP) stop layer between the low-k dielectric layer and the etch stop layer.