Semiconductor device

Abstract

A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the p-type Si substrate so that it surrounds the p-type well region. A plurality of conductive regions which pierce through the n-type well region are formed at regular intervals. By doing so, parasitic resistance from the p-type Si substrate, through the plurality of conductive regions, to the n-type MOS transistors becomes low. Accordingly, when back bias is applied to a contact region, the back bias potential of the n-type MOS transistors can be controlled uniformly. As a result, the influence of noise from the p-type Si substrate or the p-type well region can be reduced.

1 . A semiconductor device comprising:
 a semiconductor substrate of a first conduction type;   a first well region of the first conduction type formed beneath a surface of the semiconductor substrate;   transistors formed on the first well region;   a second well region of a second conduction type formed in the semiconductor substrate to surround the first well region; and   a plurality of conductive regions of the first conduction type which pierce through the second well region and which are arranged so as to make parasitic resistance from the semiconductor substrate to the transistors not extremely high, irrespective of positions of the transistors, but approximately equal.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the plurality of conductive regions are arranged at regular intervals. 
     
     
         3 . The semiconductor device according to  claim 2 , wherein the plurality of conductive regions are arranged like a honeycomb or a grid. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the plurality of conductive regions are formed densely in part or all of edge portions of the second well region, compared with a middle portion of the second well region. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein a shape of the first well region is like a belt, a cross, the letter “L,” or the letter “T” from a top view. 
     
     
         6 . The semiconductor device according to  claim 5 , wherein if the shape of the first well region is like a cross, the letter “L,” or the letter “T” from the top view, the plurality of conductive regions are arranged at least in the second well region directly beneath a cross portion of the shape. 
     
     
         7 . The semiconductor device according to  claim 1 , further comprising a contact region formed on a surface of the semiconductor substrate for supplying back bias to the first well region via the plurality of conductive regions, wherein arrangement of the plurality of conductive regions is determined on the basis of distance from the contact region to the transistors. 
     
     
         8 . The semiconductor device according to  claim 1 , further comprising:
 other transistors which are formed on the first well region and which are different from the transistors; and   other plural conductive regions of the first conduction type, in addition to the plurality of conductive regions, which pierce through the second well region and which are arranged so as to make parasitic resistance from the semiconductor substrate to the other transistors equal.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein the transistors differ from the other transistors in operation speed. 
     
     
         10 . The semiconductor device according to  claim 8 , wherein compared with the other plural conductive regions, the plurality of conductive regions are formed densely in the second well region.