Method and manufacturing low leakage MOSFETs and FinFETs

Abstract

By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

1 . A method of fabricating an integrated circuit (IC) device, the method comprising: 
 providing a substrate having at least an uppermost portion comprised of a crystalline semiconducting material;    forming a source region on the uppermost portion of the substrate, the source region being doped with a first dopant having a first type of majority carrier;    forming a drain region, the drain region being doped with a second dopant supporting a same-type majority carrier as the first dopant, the drain region being aligned with the source region such that any source-drain current flows substantially parallel to a {100} plane of the crystalline semiconducting material portion of the substrate, the drain region being coupled to the source region by a channel region within the uppermost portion of the substrate; and    forming a gate region, the gate region having a third dopant, the third dopant supporting a majority carrier of opposite polarity to that of the first dopant, the gate region overlying the channel region, the gate region further being coupled to the channel region by a dielectric layer.    
   
   
       2 . The method of  claim 1  wherein the substrate is selected to be an elemental semiconductor.  
   
   
       3 . The method of  claim 2  wherein the elemental semiconductor is selected to be silicon.  
   
   
       4 . The method of  claim 1  wherein the substrate is selected to be a compound semiconductor.  
   
   
       5 . The method of  claim 1  wherein the substrate is selected to be silicon-on-insulator (SOI).  
   
   
       6 . The method of  claim 1  wherein the substrate is selected to be oxygen-implanted silicon (SIMOX).  
   
   
       7 . The method of  claim 1  wherein the crystalline semiconducting material is selected to be comprised substantially of silicon.  
   
   
       8 . An integrated circuit (IC) device comprising: 
 a substrate having at least an uppermost portion comprised of a crystalline semiconducting material;    a source region on the uppermost portion of the substrate having a first doped region, the first doped region supporting a first type of majority carrier;    a drain region having a second doped region, the second doped region supporting the first type of majority carrier, the drain region being aligned with the source region such that any source-drain current flows substantially parallel to a {100} plane of the crystalline material portion of the substrate; and    a gate region, the gate region being coupled to the channel region by a dielectric layer.    
   
   
       9 . The IC device of  claim 8  wherein the substrate is an elemental semiconductor.  
   
   
       10 . The IC device of  claim 9  wherein the elemental semiconductor is silicon.  
   
   
       11 . The IC device of  claim 8  wherein the substrate is a compound semiconductor.  
   
   
       12 . The IC device of  claim 8  wherein the substrate is silicon-on-insulator (SOI).  
   
   
       13 . The IC device of  claim 8  wherein the substrate is oxygen-implanted silicon (SIMOX).  
   
   
       14 . The IC device of  claim 8  wherein the crystalline semiconducting material is comprised substantially of silicon.  
   
   
       15 . A method for forming an integrated circuit (IC) device, the method comprising: 
 providing a substrate having at least an uppermost portion comprised of a crystalline semiconducting material;    forming a fin on the uppermost portion of the substrate, the fin having a given width and length, the fin arranged such that the length of the fin is aligned substantially parallel to a {100} plane of the crystalline semiconducting material portion of the substrate;    forming a dielectric layer over the fin;    forming a gate region over the dielectric layer, the gate region covering a channel, the channel being doped with a material to support a first type of majority carrier; and    doping portions of the fin not covered by the gate region, the dopant supporting a second type of majority carrier.    
   
   
       16 . The method of  claim 15  wherein the substrate is selected to be an elemental semiconductor.  
   
   
       17 . The method of  claim 16  wherein the elemental semiconductor is selected to be silicon.  
   
   
       18 . The method of  claim 15  wherein the substrate is selected to be a compound semiconductor.  
   
   
       19 . The method of  claim 15  wherein the substrate is selected to be silicon-on-insulator (SOI).  
   
   
       20 . The method of  claim 15  wherein the substrate is selected to be oxygen-implanted silicon (SIMOX).  
   
   
       21 . The method of  claim 15  wherein the crystalline semiconductor material is selected to be comprised substantially of silicon.  
   
   
       22 . An integrated circuit (IC) device, comprising: 
 a substrate having at least an uppermost portion comprised of a crystalline semiconducting material;    a fin, the fin having a given width and length, the fin arranged such that a current path of the fin is substantially parallel to a {100} plane of the crystalline semiconducting material, the fin further comprising: 
 a source region, the source region being doped with a first dopant which supports a first type of majority carrier;  
 a drain region, the drain region being doped with a second dopant which supports the first type of majority carrier; and  
 a channel region, the channel region being interposed between the source region and the drain region; and  
   a gate region, the gate region being formed on at least three sides of the channel region, the gate region being separated from the channel region by a thin dielectric layer, the gate region being doped with a dopant which supports a second type of majority carrier.    
   
   
       23 . The IC device of  claim 22  wherein the substrate is silicon-on-insulator (SOI).  
   
   
       24 . The IC device of  claim 22  wherein the substrate is oxygen-implanted silicon (SIMOX).  
   
   
       25 . The IC device of  claim 22  wherein the crystalline semiconducting material is comprised substantially of silicon.  
   
   
       26 . A method of fabricating an integrated circuit (IC) device, the method comprising: 
 providing a substrate having at least an uppermost portion comprised of a crystalline semiconducting material;    providing an area for forming a source region on a first surface of the uppermost portion of the substrate;    providing an area for forming a drain region in proximity to the source region area, the drain region area being aligned with the source region area such that any source-drain current generated flows substantially parallel to a {100} plane of the crystalline semiconducting material portion of the substrate, the drain region being coupled to the source region by a channel region area within the first surface of the uppermost portion of the substrate; and    providing an area for forming a gate region, the gate region area overlying the channel region, the gate region area being coupled to the channel region by a dielectric layer.    
   
   
       27 . The method of  claim 26  further comprising forming shallow trench isolation features on the first surface of the semiconducting material.  
   
   
       28 . The method of  claim 27  wherein the shallow trench isolation features are formed by: 
 etching a trench into the uppermost portion of the crystalline semiconducting material; and    filling the trench with a dielectric fill material.    
   
   
       29 . The method of  claim 27  further comprising locating the shallow trench isolation feature between active areas located on the first surface of the uppermost portion of the substrate.  
   
   
       30 . The method of  claim 26  wherein the substrate is selected to be an elemental semiconductor.  
   
   
       31 . The method of  claim 30  wherein the elemental semiconductor is selected to be silicon.  
   
   
       32 . The method of  claim 26  wherein the substrate is selected to be silicon-on-insulator (SOI).  
   
   
       33 . A method of fabricating an integrated circuit (IC) device, the method comprising: 
 providing a substrate having at least an uppermost portion comprised of a crystalline semiconducting material;    providing an area for forming a source region on a first surface of the uppermost portion of the substrate;    providing an area for forming a drain region in proximity to the source region area; and    locating the source area and the drain area with respect to each other such that a line drawn between them is substantially orthogonal to a [100] direction of the crystalline semiconducting material.    
   
   
       34 . The method of  claim 33  wherein the step of locating the source area and the drain area further includes aligning the drain region area with the source region area such that any source-drain current generated flows substantially parallel to a {100} plane of the crystalline semiconducting material portion of the substrate.  
   
   
       35 . The method of  claim 34  further comprising: 
 coupling the drain region to the source region by forming a channel region within the first surface of the uppermost portion of the substrate; and    providing an area for forming a gate region, the gate region overlying the channel region, the gate region area being coupled to the channel region by forming a dielectric layer.    
   
   
       36 . The method of  claim 33  further comprising forming shallow trench isolation features on the first surface of the semiconducting material.  
   
   
       37 . The method of  claim 36  wherein the shallow trench isolation features are formed by: 
 etching a trench into the uppermost portion of the crystalline semiconducting material; and    filling the trench with a dielectric fill material.    
   
   
       38 . The method of  claim 36  further comprising locating the shallow trench isolation feature between active areas located on the first surface of the uppermost portion of the substrate.  
   
   
       39 . An integrated circuit (IC) device comprising: 
 a substrate having at least an uppermost portion comprised of a crystalline semiconducting material;    a source region on the uppermost portion of the substrate; and    a drain region located in proximity to the source region and aligned with the source region such that a line drawn between the source region and the drain region is substantially orthogonal to a [100] direction of the crystalline semiconducting material.    
   
   
       40 . The integrated circuit (IC) device of  claim 39 , further comprising a channel region interposed between the source region and the drain region, the channel region being aligned that any source-drain current flowing through the channel region flows substantially parallel to a {100} plane of the crystalline material portion of the substrate.  
   
   
       41 . The integrated circuit (IC) device of  claim 39  further comprising a gate region coupled to the channel region by a dielectric layer.  
   
   
       42 . The integrated circuit (IC) device of  claim 39  wherein the substrate is an elemental semiconductor.  
   
   
       43 . The integrated circuit (IC) device of  claim 42  wherein the elemental semiconductor is silicon.  
   
   
       44 . The integrated circuit (IC) device of  claim 39  wherein the substrate is a compound semiconductor.  
   
   
       45 . The IC integrated circuit (IC) device of  claim 39  wherein the substrate is silicon-on-insulator (SOI).  
   
   
       46 . The IC integrated circuit (IC) device of  claim 39  wherein the substrate is oxygen-implanted silicon (SIMOX).  
   
   
       47 . The integrated circuit (IC) device of  claim 39  wherein the crystalline semiconducting material is comprised substantially of silicon.  
   
   
       48 . An integrated circuit (IC) device, comprising: 
 a substrate having at least an uppermost portion comprised of a crystalline semiconducting material;    a fin, the fin having a given width and length with rounded uppermost edges, the fin arranged such that a current path of the fin is substantially parallel to a {100} plane of the crystalline semiconducting material, the fin further comprising: 
 a source region, a drain region, and a channel region, the channel region being interposed between the source region and the drain region; and  
 a gate region, the gate region being formed on at least three sides of the channel region, the gate region being separated from the channel region by a thin dielectric layer.  
   
   
   
       49 . The integrated circuit (IC) device of  claim 48  wherein the substrate is silicon-on-insulator (SOI).  
   
   
       50 . The integrated circuit (IC) device of  claim 48  wherein the substrate is oxygen-implanted silicon (SIMOX).  
   
   
       51 . The IC device of  claim 48  wherein the crystalline semiconducting material is comprised substantially of silicon.