Method and apparatus for enhancing cryptographic engines against security attacks

Abstract

Apparatus, systems and methods for enhancing cryptographic engines against attack are disclosed. In one implementation, a method is disclosed including limiting a cryptographic device to a first number of cryptographic operations, and reconfiguring the cryptographic device to limit the cryptographic device to a second number of cryptographic operations. Additional implementations are disclosed.

1 . A method comprising: 
 limiting a cryptographic device to a first number of cryptographic operations; and    reconfiguring the cryptographic device to limit the cryptographic device to a second number of cryptographic operations.    
   
   
       2 . The method of  claim 1 , wherein the cryptographic operations include decryption of an encrypted storage key.  
   
   
       3 . The method of  claim 1 , wherein reconfiguring comprises providing a configuration payload to the cryptographic device, the configuration payload specifying the second number.  
   
   
       4 . The method of  claim 3 , wherein the configuration payload further specifies changes to storage keys or secrets associated with the cryptographic device.  
   
   
       5 . The method of  claim 1 , further comprising: 
 preventing the cryptographic device from undertaking further cryptographic operations if the cryptographic device exceeds the second number of cryptographic operations.    
   
   
       6 . The method of  claim 5 , wherein preventing the cryptographic device from undertaking further cryptographic operations comprises one of disabling the cryptographic device, resetting a processor that supports the cryptographic device, or halting, at least in part, the operation of a system that supports the cryptographic device.  
   
   
       7 . The method of  claim 1 , wherein limiting the cryptographic device to a second number of cryptographic operations includes limiting the cryptographic device to cryptographic operations within a time interval.  
   
   
       8 . An apparatus comprising: 
 a cryptographic engine at least capable of encrypting data and decrypting data; and    a limiter coupled to the cryptographic engine, the limiter at least capable of limiting the number of cryptographic operations the cryptographic engine may undertake, wherein the limiter is configurable to limit the cryptographic engine to different numbers of cryptographic operations.    
   
   
       9 . The apparatus of  claim 8 , wherein the cryptographic operations include decryption of an encrypted storage key.  
   
   
       10 . The apparatus of  claim 8 , further comprising: 
 one time programmable memory for storing a public key to be used by the cryptographic engine.    
   
   
       11 . The apparatus of  claim 8 , wherein the limiter includes an operation counter coupled to the cryptographic engine, the operation counter at least capable of counting the number of cryptographic operations undertaken by the cryptographic engine.  
   
   
       12 . The apparatus of  claim 8 , wherein the limiter is further configurable to change storage keys or secrets associated with the cryptographic engine.  
   
   
       13 . The apparatus of  claim 8 , wherein limiting the number of cryptographic operations the cryptographic engine may undertake comprises one of disabling the cryptographic engine, resetting a processor that supports the cryptographic engine, or halting, at least in part, the operation of a system that supports the cryptographic engine.  
   
   
       14 . A system comprising: 
 a cryptographic engine at least capable of encrypting data and decrypting data;    a limiter coupled to the cryptographic engine, the limiter at least capable of limiting the number of cryptographic operations the cryptographic engine may undertake, wherein the limiter is configurable to limit the cryptographic engine to different numbers of cryptographic operations; and    a display processor at least capable of processing the decrypting data for display.    
   
   
       15 . The system of  claim 14 , wherein the cryptographic operations include decryption of an encrypted storage key.  
   
   
       16 . The system of  claim 14 , wherein the limiter includes an operation counter coupled to the cryptographic engine, the operation counter at least capable of counting the number of cryptographic operations undertaken by the cryptographic engine.  
   
   
       17 . The system of  claim 14 , wherein the limiter is further configurable to change storage keys or secrets associated with the cryptographic engine.  
   
   
       18 . The system of  claim 14 , further comprising: 
 one time programmable memory for storing a public key to be used by the cryptographic engine.    
   
   
       19 . The system of  claim 14 , wherein limiting the number of cryptographic operations the cryptographic engine may undertake comprises one of disabling the cryptographic engine, resetting a processor that supports the cryptographic engine, or halting, at least in part, the operation of a system that supports the cryptographic engine.