Auto gain controller

Abstract

A gain-controlled transimpedance amplifier circuit that comprises a first gain unit including an input for receiving a first current and an output, a current source for providing a second current, a second gain unit including an input and an output, a first impedance unit of a first impedance coupled in parallel with the second gain unit, and a comparator including an output, a first input coupled to the output of the first gain unit, and a second input coupled to the output of the second gain unit.

1 . A gain-controlled transimpedance amplifier circuit, comprising: 
 a first gain unit including an input for receiving a first current and an output;    a current source for providing a second current;    a second gain unit including an input and an output;    a first impedance unit of a first impedance coupled in parallel with the second gain unit; and    a comparator including an output, a first input coupled to the output of the first gain unit, and a second input coupled to the output of the second gain unit,    wherein the first gain unit includes complementary metal-oxide-semiconductor (CMOS) inverters, each of the CMOS inverters having a same W P /W N  ratio, wherein W P  is a channel width of a p-type MOS (PMOS) transistor of one of the CMOS inverters, and W N  is a channel width of an n-type MOS (NMOS) transistor of the CMOS inverter.    
   
   
       2 . The circuit of  claim 1 , wherein the second gain unit includes a CMOS inverter having the same W P /W N  ratio as each of the CMOS inverters of the first gain unit.  
   
   
       3 . The circuit of  claim 1 , further comprising: 
 a second impedance unit including NMOS transistors corresponding to the CMOS inverters of the first gain unit,    wherein a channel width ratio among the NMOS transistors of the second impedance unit is equal to a channel width ratio among the corresponding NMOS transistors of the CMOS inverters.    
   
   
       4 . The circuit of  claim 3 , wherein a channel width of one of the NMOS transistors of the second impedance unit is greater than a channel width of the other NMOS transistors of the second impedance unit.  
   
   
       5 - 12 . (canceled)