Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same

Abstract

A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages. Furthermore, the manufacturing processes include two half-etching steps to form the half-etched leadframe where a second half-etching step is performed after forming the encapsulant and before forming the electroplated layer.

1 . A leadless semiconductor package comprising:
 a half-etched leadframe having a plurality of leads and a plurality of outer pads integrally connected to the leads;   a chip electrically connected to the leads;   an encapsulant encapsulating the chip and the leads, wherein the encapsulant has a plurality of cavities reaching to the outer pads; and   an electroplated layer formed on the outer pads and embedded in the cavities.   
     
     
         2 . The leadless semiconductor package of  claim 1 , wherein the diameters of the cavities of the encapsulant are smaller than the ones of the outer pads to define the exposed area of the outer pads. 
     
     
         3 . The leadless semiconductor package  claim 1 , wherein the leadframe further has a die pad for attaching the chip. 
     
     
         4 . The leadless semiconductor package of  claim 2 , wherein the encapsulant further has an opening to partially expose a bottom surface of the die pad, and the electroplated layer is further formed on the exposed bottom surface. 
     
     
         5 . The leadless semiconductor package of  claim 3 , wherein the leadframe further has a plurality of tie bars connecting to the die pad and completely encapsulated by the encapsulant. 
     
     
         6 . The leadless semiconductor package of  claim 1 , wherein the depths of the cavities of the encapsulant range between 0.05 mm and 0.2 mm. 
     
     
         7 . The leadless semiconductor package of  claim 1 , wherein the materials of the electroplated layer are selected from a group consisting of nickel-gold, tin, nickel-palladium-gold, tin-lead, silver, and tin-bismuth. 
     
     
         8 . The leadless semiconductor package of  claim 1 , further comprising a plurality of solder balls bonded to the outer pads through the cavities. 
     
     
         9 . The leadless semiconductor package of  claim 1 , wherein the outer pads are ball pads. 
     
     
         10 . The leadless semiconductor package of  claim 1 , wherein the outer pads are arranged in multiple-row and staggered. 
     
     
         11 . A manufacturing process of a leadless semiconductor packages, comprising the steps of:
 providing a leadframe having a plurality of leads and a plurality of outer pads integrally connected to the leads;   performing a first half-etching step to half-etch bottom surfaces of the leads;   disposing a chip and electrically connecting the chip to the leads;   forming an encapsulant encapsulating the chip and the leads but exposing the outer pads;   performing a second half-etching step to half-etch the bottom surfaces of the outer pads so that the encapsulant has a plurality of cavities reaching to the outer pads; and   forming an electroplated layer on the outer pads embedded in the cavities.   
     
     
         12 . The manufacturing process of  claim 11 , wherein during the first half-etching, the peripheries of the bottom surface of the outer pads are half-etched simultaneously so that the diameters of the cavities formed in the second half-etching are smaller than the ones of the outer pads to define the exposed area of the outer pads. 
     
     
         13 . The manufacturing process of  claim 11 , wherein the half-etched leadframe further has a die pad for attaching the chip. 
     
     
         14 . The manufacturing process of  claim 13 , wherein during the second half-etching, the bottom surface of the die pad are half-etched simultaneously so that the encapsulant further has an opening. 
     
     
         15 . The manufacturing process of  claim 13 , wherein the leadframe further has a plurality tie bars connected to the die pad and during the first half-etching, bottom surfaces of the tie bars are half-etched simultaneously so that the encapsulant completely encapsulates the tie bars. 
     
     
         16 . The manufacturing process of  claim 11 , wherein the depths of the cavities of the encapsulant range between 0.05 mm and 0.2 mm. 
     
     
         17 . The manufacturing process of  claim 11 , wherein the materials of the electroplated layer are selected from a group consisting of nickel-gold, tin, nickel-palladium-gold, tin-lead, silver, tin-bismuth. 
     
     
         18 . The manufacturing process of  claim 11 , further comprising a step of bonding a plurality of solder balls to the outer pads through the cavities. 
     
     
         19 . The manufacturing process of  claim 18 , wherein the outer pads are ball pads. 
     
     
         20 . The manufacturing process of  claim 11 , wherein the lengths of the leads are not equal so that the outer pads can be arranged in multiple-row and staggered.