Method for Forming Ferroelectric Memory Capacitor

Abstract

A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer ( 70 ). Using the patterned hard mask layer ( 255 ), the layers are etched to form an etched barrier layer ( 205 ), and etched first metal layer ( 215 ), and etched ferroelectric layer ( 225 ), and etched second metal layers ( 235, 245 ). The etched layers form a ferroelectric memory capacitor ( 270 ) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer ( 70 ) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

1 . A ferroelectric memory cell, comprising: 
 a dielectric layer comprising an upper surface that forms a plane;    a metal contact formed in said dielectric layer;    a ferroelectric capacitor formed over said metal contact comprising: 
 a barrier layer;  
 a first metal layer;  
 a ferroelectric layer; and  
 a second metal layer wherein said ferroelectric capacitor has sidewalls such that the angle formed between said sidewalls and said plane is between 78° and 88°.  
   
   
   
       2 . The ferroelectric capacitor of  claim 1  wherein said sidewalls are formed by etching said barrier layer, first metal layer, said ferroelectric layer and said second metal layer with plasma processes at temperatures between 200° C. and 500° C.  
   
   
       3 . The ferroelectric capacitor of  claim 2  wherein said ferroelectric layer comprises PZT.  
   
   
       4 . The ferroelectric capacitor of  claim 3  wherein said PZT layer is etch using BCl 3  and Cl 2  in the ratios from 1:4 to 6:1 respectively.