Semiconductor device having a gate with a thin conductive layer

Abstract

A semiconductor device having a gate with a thin conductive layer is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer, quantum confinement of carriers within conductive layer can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane from the Fermi level. Thus, the undesirable leakage current in the device can be reduced. Additional conductive layers may be used to provide more carriers.

1 - 28 . (canceled)  
     
     
         29 . A method for forming a semiconductor device, comprising: 
 providing a semiconductor substrate;    forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer is characterized as a gate dielectric;    forming a first conductive layer on the first dielectric layer, wherein the first conductive layer has a thickness of at most approximately 4 nanometers;    forming second dielectric layer on the first conductive layer;    forming a second conductive layer on the second dielectric layer; and    forming a conductive contact electrically coupled to the first conductive layer and the second conductive layer.    
     
     
         30 . The method of  claim 29 , wherein the semiconductor device comprises a channel region under the gate dielectric, wherein the second dielectric layer on the first conductive layer extends along a length of the channel region.  
     
     
         31 . The method of  claim 29 , wherein the thickness of the first conductive layer is at most approximately 3 nanometers.  
     
     
         32 . The method of  claim 29 , wherein the thickness of the first conductive layer is at most approximately 2 nanometers.  
     
     
         33 . The method of  claim 29 , wherein the second dielectric is characterized as an interlayer dielectric (ILD) layer.  
     
     
         34 - 35 . (canceled)  
     
     
         36 . The method of  claim 29 , further comprising: 
 forming a third dielectric layer over the second conductive layer, wherein the third dielectric layer is characterized as an ILD layer.    
     
     
         37 . The method of  claim 29 , wherein the first conductive layer comprises a metal.  
     
     
         38 . A method for forming a semiconductor device, comprising: 
 providing a semiconductor substrate;    forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer is characterized as a gate dielectric;    forming a first conductive layer on the first dielectric layer, wherein the first conductive layer has a thickness of at most approximately 4 nanometers;    forming a second dielectric layer on the first conductive layer;    forming a second conductive layer in direct contact with the second dielectric layer and electrically coupled to the first conductive layer; and    forming a conductive contact electrically coupled to the first conductive layer and the second conductive layer.    
     
     
         39 . A method as in  claim 38 , further comprising: 
 forming a third dielectric layer over the second conductive layer.    
     
     
         40 . A method as in  claim 39 , wherein the third dielectric layer is characterized as an ILD layer.  
     
     
         41 . A method as in  claim 38 , further comprising forming a channel region under the gate dielectric, wherein the second dielectric layer on the first conductive layer extends along a length of the channel region.  
     
     
         42 . A method as in  claim 38 , wherein the thickness of the first conductive layer is at most approximately 3 nanometers.  
     
     
         43 . A method as in  claim 38 , wherein the thickness of the first conductive layer is at most approximately 2 nanometers.  
     
     
         44 . A method as in  claim 38 , wherein the first conductive layer comprises a first metal and the second conductive layer comprises a second metal.  
     
     
         45 . A method as in  claim 44 , wherein the first metal and the second metal are a same metal.  
     
     
         46 . A method for forming a semiconductor device, comprising: 
 providing a semiconductor substrate;    forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer is characterized as a gate dielectric, and wherein an interface between the first dielectric layer and the semiconductor substrate defines an interfacial plane;    forming a first conductive layer on the first dielectric layer, wherein the first conductive layer forms a quantization filter for carriers in a direction that is normal to the interfacial plane;    forming a second dielectric layer on the first conductive layer;    forming a second conductive layer on the second dielectric layer; and    forming a conductive contact electrically coupled to the first conductive layer and the second conductive layer.    
     
     
         47 . A method as in  claim 46 , further comprising forming a channel region under the gate dielectric, wherein the second dielectric layer on the first conductive layer extends along a length of the channel region.  
     
     
         48 . A method as in  claim 46 , wherein the thickness of the first conductive layer is at most approximately 4 nanometers.  
     
     
         49 . A method as in  claim 46 , wherein the thickness of the first conductive layer is at most approximately 2 nanometers.  
     
     
         50 . A method as in  claim 46 , further comprising forming a third dielectric layer over the second conductive layer.