Low-voltage reading device in particular for MRAM memory

Abstract

The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.

1 . Circuit for reading at least one semiconductor memory cell connected to a bit lane, including at least one first reference line, a first transistor for controlling the bit line, a second transistor for controlling the reference line, a current mirror circuit including at least one reference transistor connected to the reference line by means of the second control transistor and a write transistor of the current fixed by the reference transistor connected to the bit line by means of the first control transistor, wherein the current mirror circuit makes it possible to compare, during a memory reading phase, the discharge current of the bit line and the discharge current of the reference line, a first intermediate transistor, a gate of which is connected to a fixed potential, is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor, a gate of which is connected to the same fixed potential, is connected to the reference transistor parallel to the first control transistor by being inserted between the gate and the drain of the reference transistor, with first and second polarization transistors, a gate of which i s connected to the same polarization potential, are connected in series to the first and second intermediate transistors, respectively, enabling a constant polarization current to be superimposed on the current fixed by the reference transistor.  
   
   
       2 . Circuit according to  claim 1 , further comprising a second reference line, connected in short circuit to the first reference line, wherein the first and second reference lines correspond respectively to a memory cell place in a low logic state and a memory cell placed in a high logic state.  
   
   
       3 . Circuit according to  claim 2 , further comprising a third transistor for controlling the second reference line, wherein the current mirror circuit includes a second reference transistor a gate of which is connected to the gate of the first reference transistor, the second reference transistor is connected to the second reference line by means of the third control transistor, a third intermediate transistor a gate of which is connected to same said fixed potential is connected to the second reference transistor parallel to the third control transistor, and a third polarization transistor a gate of which is connected to same said polarization potential is connected in series to the third intermediate transistor.  
   
   
       4 . Circuit according to  claim 1 , wherein the control transistors and the polarization transistors are MOS transistors of a first conductivity and the transistors of the current mirror circuit and the intermediate transistors are MOS transistors of a second conductivity type.  
   
   
       5 . Circuit according to  claim 4 , wherein the first type of conductivity is type N and the second type of conductivity is type P.  
   
   
       6 . Circuit according to  claim 1 , further comprising an output node of which the potential varies according to the difference between the current fixed by the reference transistor and the discharge current of the bit line, enabling the programming state of the memory cell to be determined, by comparison with the potential of a reference node representative of a memory cell in a reference logic state, wherein the output node is located between the first intermediate transistor and the first polarization transistor, and the reference node is located between the second intermediate transistor and the second polarization transistor or the third intermediate transistor and the third polarization transistor.  
   
   
       7 . Circuit according to  claim 1 , wherein the circuit operates at a low supply voltage, of around several hundred millivolts.  
   
   
       8 . Integrated circuit memory including at least one read-out circuit according to  claim 1 .  
   
   
       9 . Memory according to  claim 8 , wherein the memory is a MRAM memory.  
   
   
       10 . Integrated circuit including a read-out circuit or a memory according to  claim 1.