Method for manufacturing semiconductor device having plural electroconductive plugs

Abstract

The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit line 6 electrically coupled to the cell contact 9 is formed of the material, which is same as the material of cell contact 9 . In the process for forming the bit line 6 on the cell contact interlayer film 8 by etching, the etching for creating an upper surface of the cell contact 9 that is not coupled to the bit line 6 being lower than an upper surface of the cell contact 9 that is coupled to the bit line 6 . Further, after the formation of the bit line 6 , the barrier metal layer 5 formed on the lower surface of the bit line 6 is selectively etched.

1 . A method for manufacturing a semiconductor device having a capacitive element on an upper portion of a transistor formed on a semiconductor substrate for coupling to said transistor, comprising: 
 forming a transistor on a semiconductor substrate;    forming a first interlayer insulating film covering said transistor;    forming in said first interlayer insulating film a first electroconducting plug and a second electroconducting plug that couple to said transistor;    forming on said first interlayer insulating film an interconnect being coupled to said first electroconducting plug;    etching said second electroconducting plug to create an upper surface of said second electroconducting plug that is disposed lower than an upper surface of said first electroconducting plug;    forming a second interlayer insulating film on said first interlayer insulating film to cover said interconnect;    forming in said second interlayer insulating film a third electroconducting plug being coupled to said second electroconducting plug; and    forming on said second interlayer insulating film a capacitive element being coupled to said second electroconducting plug.    
   
   
       2 . The method according to  claim 1 , wherein: said first interlayer insulating film is a cell contact interlayer film; said first electroconducting plug and said second electroconducting plug are cell contacts; said interconnect is a bit line; said second interlayer insulating film is a capacitive contact interlayer film; and said third electroconducting plug is a capacitive contact.  
   
   
       3 . The method according to  claim 1 , wherein said forming said interconnect comprises: 
 forming said interconnect comprising the material that constitutes said second electroconducting plug.    
   
   
       4 . The method according to  claim 1 , wherein said forming said second electroconducting plug comprises forming said second electroconducting plug comprising a multi-layered member including a layer containing tungsten and a layer containing titanium nitride, and wherein said forming said interconnect comprises forming said interconnect comprising a multi-layered member including a layer containing tungsten and a layer containing titanium nitride.  
   
   
       5 . The method according to  claim 1 , wherein said forming said interconnect comprises forming said interconnect containing a barrier metal layer and an electrically conducting layer disposed on said barrier metal layer, and wherein said method further comprises selectively etching said barrier metal layer after forming said interconnect.  
   
   
       6 . The method according to  claim 1 , wherein said forming said interconnect comprises: 
 forming on said first interlayer insulating film a multi-layered film that comprises a barrier metal layer and an electrically conducting layer disposed on said barrier metal layer;    patterning said electrically conducting layer by etching said electrically conducting layer with a first etch gas; and    patterning said barrier metal layer by etching said barrier metal layer with a second etch gas,    and wherein said etching said second electroconducting plug comprises:    etching a portion in vicinity of the upper surface of said second electroconducting plug with a third etch gas to create an upper surface of said second electroconducting plug being lower than an upper surface of said first electroconducting plug.    
   
   
       7 . The method according to  claim 1 , wherein said forming said interconnect comprises: 
 forming on the said first interlayer insulating film a multi-layered film that comprises a barrier metal layer and an electrically conducting layer disposed on said barrier metal layer; and    patterning said multi-layered film by etching said electrically conducting layer and said barrier metal layer with a first etch gas, and    wherein said etching said second electroconducting plug comprises:    etching a portion in vicinity of the upper surface of said second electroconducting plug with a second etch gas to create an upper surface of said second electroconducting plug being lower than an upper surface of said first electroconducting plug.    
   
   
       8 . The method according to  claim 1 , wherein said forming said interconnect comprises: 
 forming on the said first interlayer insulating film a multi-layered film that comprises a barrier metal layer and an electrically conducting layer disposed on said barrier metal layer; and    patterning said multi-layered film by etching said electrically conducting layer and said barrier metal layer with an etch gas, and    wherein said etching said second electroconducting plug comprises: 
 etching a portion in vicinity of the upper surface of said second electroconducting plug with said etch gas to create an upper surface of said second electroconducting plug being lower than an upper surface of said first electroconducting plug.  
   
   
   
       9 . A method for manufacturing a semiconductor device having an element on an upper layer of a transistor formed on a semiconductor substrate for electrically coupling to said transistor, comprising: 
 forming a transistor on a semiconductor substrate;    forming a first contact interlayer film covering said transistor;    forming a plurality of first contacts in said first contact interlayer film for electrically coupling to said transistor;    forming on said first contact interlayer film an interconnect electrically coupled to said first contact and etching thereof so that an upper surface of said plurality of first contact, which is not coupled to said interconnect, is lower than an upper surface of said plurality of first contact, which is coupled to said interconnect;    forming a second contact interlayer film on said first contact interlayer film to cover said interconnect;    forming a second contact on said second contact interlayer film for electrically coupling thereof to said first contact; and    forming an element on said second contact interlayer film for electrically coupling to said second contact.