Substrate-based silicon diode for electrostatic discharge protection

Abstract

An integrated circuit device is disclosed that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, and a first isolation structure formed inside the well region. Further, a second isolation structure is formed inside the well region and spaced apart from the first isolation structure, a dielectric layer is formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion, and a center portion is disposed between the p-type and n-type portions.

1 . A method for protecting a silicon-on-insulator device from electrostatic discharge, comprising the steps of: 
 providing a signal to the device through a silicon-on-insulator circuit;    providing a base-biased silicon diode in the silicon-on-insulator circuit; and    protecting the device from electrostatic discharge with the base-biased silicon diode.    
     
     
         2 . A method for protecting a complementary metal-oxide semiconductor device from electrostatic discharge, comprising the steps of: 
 providing a signal to the device through a complementary metal-oxide semiconductor circuit;    providing a substrate-biased silicon diode in the complementary metal-oxide semiconductor circuit; and    protecting the device from electrostatic discharge produced from the signal with the substrate-biased silicon diode.    
     
     
         3 . A method for forming a silicon diode, comprising the steps of: 
 forming a first silicon layer;    forming a first isolation structure and a second isolation structure inside the first silicon layer, the first isolation structure being spaced apart from the second isolation structure;    forming a dielectric layer over the first silicon layer;    forming a second silicon layer over the dielectric layer;    forming dielectric spacers contiguous with the second silicon layer;    implanting a first impurity having a first concentration into a first portion and a second portion of the second silicon layer, the first portion being contiguous with the second portion and the second portion overlapping a region of the first silicon layer between the first isolation structure and the second isolation structure;    implanting a first impurity having a second concentration into the first portion of the second silicon layer, wherein the second concentration is greater than the first concentration; and    implanting a second impurity into a third portion of the second silicon layer, wherein the third portion is contiguous with the second portion.    
     
     
         4 . The method as claimed in  claim 3 , wherein the silicon layer is a semiconductor substrate.  
     
     
         5 . The method as claimed in  claim 3 , further comprising a step of forming a well region inside the semiconductor substrate, wherein the first and second isolation structures are disposed inside the well region.  
     
     
         6 . The method as claimed in  claim 3 , wherein the first impurity is an n-type impurity and the second impurity is a p-type impurity.  
     
     
         7 . The method as claimed in  claim 3 , wherein the first impurity is a p-type impurity and the second impurity is an n-type impurity.  
     
     
         8 . The method as claimed in  claim 3 , wherein the step of forming a first and second isolation structures comprises the steps of forming a first trench and a second trench spaced apart from the first trench in the silicon layer, and providing a dielectric material in the first and second trenches.  
     
     
         9 . The method as claimed in  claim 3 , wherein the step of forming a dielectric layer includes a step of growing an oxide layer.  
     
     
         10 . The method as claimed in  claim 3 , wherein the steps of implanting a first impurity, having a first concentration and implanting a first impurity having a second concentration create a diffused region adjacent one of first and second field isolation structures.  
     
     
         11 . The method as claimed in  claim 3 , wherein the step of implanting a first impurity having a first concentration includes the steps of: 
 providing a photoresist over the first silicon layer and the second silicon layer;    patterning and defining the photoresist to expose the first portion and the second portion of the second silicon layer;    implanting the first impurity into-the first portion and the second portion; and    removing the photoresist.    
     
     
         12 . The method as claimed in  claim 3 , wherein the step of implanting a second impurity includes the steps of: 
 providing a photoresist over the second silicon layer and the first silicon layer;    patterning and defining the photoresist to expose the third portion of the second silicon layer;    implanting the second impurity into the third portion; and    removing the photoresist.    
     
     
         13 . The method as claimed in  claim 3 , further comprising: 
 defining a substrate;    forming a layer of insulator over the substrate; and    forming the layer of silicon over the insulator layer.    
     
     
         14 . A method for forming a base-biased silicon diode, comprising the steps of: 
 forming a first and second isolation structures inside a silicon layer;    defining a base region inside the silicon layer, the base region being disposed between and contiguous with the first and second isolation structures;    forming a dielectric layer over the well region;    forming a layer of silicon over the dielectric layer;    implanting a first impurity having a first concentration into a first portion and a second portion of the silicon layer, wherein the first portion is contiguous with the second portion and the second portion overlapping a region of the silicon layer between the first isolation structure and the second isolation structure;    implanting a first impurity having a second concentration into the first portion and second portion of the silicon layer, wherein the second concentration is greater than the first concentration; and    implanting a second impurity into a third portion of the silicon layer, wherein the third portion is contiguous with the second portion and overlaps the second isolation structure.    
     
     
         15 . The method as claimed in  claim 14 , wherein the silicon layer is a silicon layer of a silicon-on-insulator structure.  
     
     
         16 . A method for forming a substrate-biased silicon diode, comprising the steps of: 
 forming a first isolation structure and a second isolation structure spaced apart from the first isolation structure inside a silicon layer;    forming a dielectric layer over the silicon layer;    forming a layer of silicon having two ends over the dielectric layer;    forming dielectric spacers contiguous with the two ends of the silicon layer;    implanting a first impurity having a first concentration into a first portion and a second portion of the silicon layer, wherein the first portion is contiguous with the second portion and overlaps the first isolation structure;    implanting a second impurity into a third portion of the silicon layer, wherein the third portion is contiguous with the second portion and overlaps the second isolation structure; and    implanting a first impurity having a second concentration into the first portion of the silicon layer, wherein the second concentration is greater than the first concentration.    
     
     
         17 . The method as claimed in  claim 16 , wherein the step of implanting a second impurity creates a diffused region adjacent one of first and second field isolation structures.  
     
     
         18 . An integrated circuit device used for electrostatic discharge protection, comprising: 
 a semiconductor substrate;    a dielectric layer disposed over the substrate; and    a layer of silicon, formed over the dielectric layer, including a p-type portion and an n-type portion.    
     
     
         19 . An integrated circuit device used for electrostatic discharge protection, comprising: 
 a semiconductor substrate;    a dielectric layer disposed over the substrate;    a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion, and a center portion disposed between the n-type and p-type portions.