Contact hole formation method

Abstract

A contact hole formation method includes a process of depositing a BPSG film 4 on a semiconductor substrate 1 on which transistors are formed, a process of planarizing the BPSG film 4 , a process of depositing a dielectric film 5 on the BPSG film 4 , and a process of forming contact holes 8 through the BPSG film 4 and the dielectric film 5 so as to reach the semiconductor substrate 1 , in a case in which gate electrodes are densely formed in some areas and sparsely formed in other areas. The above-described contact hole formation method allows a thickness of the BPSG film 4 to be uniform irrespective of the density of the gate electrodes, whereby an etching rate becomes uniform over the entire area of the semiconductor device. Thus, it is possible to form contact holes having minimized variations in a contact resistance and a value of leakage current.

1 - 14 . (canceled)  
   
   
       15 . A semiconductor device, comprising: 
 a substrate having an area in which gate electrodes are densely arranged and an area in which gate electrodes are sparsely arranged;    a first dielectric film on said substrate and provided with a planarized surface; and    a second dielectric film on said planarized surface of said first dielectric film and having an etching rate different from an etching rate of said first dielectric film,    wherein contact holes are formed through said first and second dielectric films.    
   
   
       16 . The semiconductor device according to  claim 15 , wherein said second dielectric film is planarized.  
   
   
       17 . The semiconductor device according to  claim 15 , wherein each of said contact holes extends to a surface or a corresponding one of said gate electrodes.  
   
   
       18 . The semiconductor device according to  claim 15 , wherein a distance between at least two adjacent ones of said gate electrodes in the area in which gate electrodes are densely arranged is at most 0.3 μm.  
   
   
       19 . The semiconductor device according to  claim 15 , wherein an entire surface of said first dielectric film is continuously higher than a top surface of said gate electrodes.  
   
   
       20 . The semiconductor device according to  claim 15 , wherein said first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.  
   
   
       21 . The semiconductor device according to  claim 15 , wherein said second dielectric film is a TEOS film or a silicon nitride film.  
   
   
       22 . A semiconductor device, comprising: 
 a substrate having an area in which interconnections are densely arranged and an area in which interconnections are sparsely arranged;    a first dielectric film on said substrate and provided with a planarized surface; and    a second dielectric film on said planarized surface of said first dielectric film and having an etching rate different from an etching rate of said first dielectric film,    wherein contact holes are formed through said first and second dielectric films.    
   
   
       23 . The semiconductor device according to  claim 22 , wherein said second dielectric film is planarized.  
   
   
       24 . The semiconductor device according to  claim 22 , wherein each of said contact holes extends to a surface or a corresponding one of said interconnections.  
   
   
       25 . The semiconductor device according to  claim 22 , wherein a distance between at least two adjacent ones of said interconnections in the area in which interconnections are densely arranged is at most 0.3 μm.  
   
   
       26 . The semiconductor device according to  claim 22 , wherein an entire surface of said first dielectric film is continuously higher than a top surface of said interconnections.  
   
   
       27 . The semiconductor device according to  claim 22 , wherein said first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.  
   
   
       28 . The semiconductor device according to  claim 22 , wherein said second dielectric film is a TEOS film or a silicon nitride film.  
   
   
       29 . A semiconductor device, comprising: 
 a substrate having thereon interconnections spaced at different intervals;    a first dielectric film on said substrate and provided with a planarized surface; and    a second dielectric film on said planarized surface of said first dielectric film and having an etching rate different from an etching rate of said first dielectric film,    wherein contact holes are formed through said first and second dielectric films.    
   
   
       30 . The semiconductor device according to  claim 29 , wherein said second dielectric film is planarized.  
   
   
       31 . The semiconductor device according to  claim 29 , wherein each of said contact holes extends to a surface or a corresponding one of said interconnections.  
   
   
       32 . The semiconductor device according to  claim 29 , wherein an entire surface of said first dielectric film is continuously higher than a top surface of said interconnections.  
   
   
       33 . The semiconductor device according to  claim 29 , wherein said first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.  
   
   
       34 . The semiconductor device according to  claim 29 , wherein said second dielectric film is a TEOS film or a silicon nitride film.