Warp-free semiconductor wafer, and devices using the same

Abstract

A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the main semiconductor region on the substrate, as well as to enhance the voltage strength of the devices made from the wafer, the counter semiconductor region is made similar in configuration to the main semiconductor region. The main semiconductor region and counter semiconductor region are arranged in bilateral symmetry as viewed in a cross-sectional plane at right angles with the substrate surfaces.

1 . A semiconductor wafer comprising:
 (a) a substrate made from material comprising silicon, the substrate having a pair of opposite major surfaces;   (b) a main semiconductor region of Groups III-V compound semiconductor material formed on one major surface of the substrate, the main semiconductor region possibly exerting a warping effect on the substrate; and   (c) a counter semiconductor region of Groups III-V compound semiconductor material formed on the other major surface of the substrate in order to counterbalance the possible warping effect of the main semiconductor region on the substrate.   
   
   
       2 . A semiconductor wafer as defined in  claim 1 , wherein the main semiconductor region and the counter semiconductor region are of the same configuration. 
   
   
       3 . A semiconductor wafer as defined in  claim 2 , wherein the main semiconductor region and the counter semiconductor region are each constituted of a plurality of compound semiconductor layers in lamination, the constituent layers of the main semiconductor region and the counter semiconductor region being disposed in mirror-image relationship to each other as viewed cross-sectionally along a plane at right angles with the major surfaces of the substrate. 
   
   
       4 . A semiconductor wafer as defined in  claim 1 , wherein the main semiconductor region and the counter semiconductor region are of the same thickness. 
   
   
       5 . A semiconductor device comprising:
 (a) a substrate made from material comprising silicon, the substrate having a pair of opposite major surfaces;   (b) a main semiconductor region of Groups III-V compound semiconductor material formed on one major surface of the substrate, the main semiconductor region being configured to provide a desired semiconductor device;   (c) a counter semiconductor region of Groups III-V compound semiconductor material formed on the other major surface of the substrate;   (d) at least two main electrodes on the main semiconductor region; and   (e) a back electrode on the counter semiconductor region.   
   
   
       6 . A semiconductor device as defined in  claim 5 , further comprising a conductor electrically connecting the back electrode to one of the two main electrodes. 
   
   
       7 . A semiconductor device as defined in  claim 6 , wherein the conductor is received via an insulator in a trench formed in the substrate and the main and the counter semiconductor region. 
   
   
       8 . A field-effect semiconductor device comprising:
 (a) a substrate made from material comprising silicon, the substrate having a pair of opposite major surfaces;   (b) a main semiconductor region of Groups III-V compound semiconductor material formed on one major surface of the substrate;   (c) a counter semiconductor region of Groups III-V compound semiconductor material formed on the other major surface of the substrate;   (d) a source, a drain and a gate on the main semiconductor region; and   (e) a back electrode on the counter semiconductor region.   
   
   
       9 . A field-effect semiconductor device as defined in  claim 8 , further comprising a conductor electrically connecting the back electrode to the source. 
   
   
       10 . A field-effect semiconductor device as defined in  claim 8 , further comprising a conductor electrically connecting the back electrode to the gate. 
   
   
       11 . A field-effect semiconductor device as defined in  claim 8 , wherein at least the main semiconductor region is a lamination of at least two compound semiconductor layers of different compositions. 
   
   
       12 . A field-effect semiconductor device as defined in  claim 8 , wherein the main semiconductor region is in the form of a single layer of a prescribed conductivity type. 
   
   
       13 . A method of fabricating a warp-free semiconductor wafer which comprises:
 (a) providing a substrate made from material comprising silicon; and   (b) concurrently forming a main semiconductor region and counter semiconductor region of Groups III-V compound semiconductor material on a pair of opposite major surfaces of the substrate.   
   
   
       14 . A method of fabricating a warp-free semiconductor wafer as defined in  claim 13 , wherein the main semiconductor region and the counter semiconductor region are each constituted of at least a first and a second compound semiconductor layer of dissimilar compositions, and wherein the main semiconductor region and the counter semiconductor region are formed by concurrently creating the first compound semiconductor layers on the pair of opposite major surfaces of the substrate and then by concurrently creating the second compound semiconductor layers on the first compound semiconductor layers.