Simulation method for semiconductor circuit device and simulator for semiconductor circuit device

Abstract

A simulator and method for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, in which when a negative bias gate voltage is applied to a gate of the transistor, characteristics of the transistor are deteriorated. When the negative bias voltage is terminated by applying a bias free voltage, the deteriorated transistor characteristics are recovered. In a deterioration period and a recovery period, a logarithm “log(t)” is obtained for an application time “t” of the gate voltage, a deterioration amount ΔP D (t)=C D +B D ·log(t) is calculated by using constants C D and B D depending on the negative bias voltage, a recovery amount ΔP R (t)=C R +B R ·log(t) is calculated by using constants C R and B R depending on the bias free voltage, and the deterioration amount (ΔP D ), the recovery amount (ΔP R ) and a basic deterioration amount (X D ) are summed.

1 - 32 . (canceled)  
   
   
       33 . A simulation method for simulating characteristics of a circuit including a metal insulator semiconductor transistor, comprising: 
 a first simulation step of performing a simulation of said circuit before deterioration of characteristics of said transistor based on a use condition of said circuit;    a second simulation step of performing a simulation of said circuit after deterioration of characteristics of said transistor based on said use condition; and    an evaluation step of evaluating characteristics of said circuit due to the deterioration by comparing a result of said first simulation step and a result of said second simulation step.    
   
   
       34 . A simulator for simulating characteristics of a circuit including a metal insulator semiconductor transistor, comprising: 
 first simulation means for performing a simulation of said circuit before deterioration of characteristics of said transistor based on a use condition of said circuit;    second simulation means for performing a simulation of said circuit after deterioration of characteristics of said transistor based on said use condition; and    evaluation means for evaluating characteristics of said circuit due to the deterioration by comparing a result of said first simulation means and a result of said second simulation means.    
   
   
       35 . The simulator as set forth in  claim 34 , further comprising recovery detection means for detecting that characteristics of said transistor are recovered to a predetermined value, wherein 
 said recovery amount calculation means sets a new gate voltage and calculates said recovery amount when said recovery detection means detects that characteristics of said transistor are recovered to a predetermined value.    
   
   
       36 . The simulator as set forth in  claim 34 , further comprising memory means, wherein 
 said memory means stores constants used in characteristics simulations of respective transistors for every gate length of the transistors by depending on a voltage between a source and a drain of each of the transistors.