Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions

Abstract

A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.

1 - 12 . (canceled)  
   
   
       13 . A method of forming a semiconductor structure, comprising: 
 providing a substrate comprising a first transistor element having a first channel region 
 and a second transistor element having a second channel region;  
   forming a first stressed layer above said first transistor element and said second transistor 
 element, said first stressed layer having a first predetermined intrinsic stress;  
   forming a second stressed layer above said first transistor element and said second 
 transistor element, said second stressed layer having a second predetermined intrinsic stress; and  
   selectively removing a portion of said second stressed layer located above said first transistor element;    wherein said second channel region is substantially unstressed and said first channel region is stressed.    
   
   
       14 . The method of  claim 13 , wherein said first transistor element is an N-type transistor and said second transistor element is a P-type transistor.  
   
   
       15 . The method of  claim 14 , wherein said first predetermined intrinsic stress is tensile and said second predetermined intrinsic stress is compressive.  
   
   
       16 . The method of  claim 13 , wherein said second stressed layer is formed above said first stressed layer.  
   
   
       17 . The method of claim  12 , wherein at least one of said first stressed layer and said second stressed layer comprises a dielectric material.  
   
   
       18 . The method of claim  12 , further comprising forming at least one first contact via through said first stressed layer and forming at least one second contact via through said first stressed layer and said second stressed layer, said first contact via being located above said first transistor element, said second contact via being located above said second transistor element.  
   
   
       19 - 24 . (canceled)  
   
   
       25 . A method of forming a semiconductor structure, comprising: 
 providing a substrate comprising a first transistor element having a first channel region and a second transistor element having a second channel region;    forming a first stressed layer above said first transistor element and said second transistor element, said first stressed layer having a first predetermined intrinsic stress;    forming a second stressed layer above said first stressed layer, said first transistor element and said second transistor element, said second stressed layer having a second predetermined intrinsic stress; and    selectively removing a portion of said second stressed layer located above said first transistor element.    
   
   
       26 . The method of  claim 25 , wherein said first transistor element is an N-type transistor and said second transistor element is a P-type transistor.  
   
   
       27 . The method of  claim 26 , wherein said first predetermined intrinsic stress is tensile and said second predetermined intrinsic stress is compressive.  
   
   
       28 . The method of  claim 25 , wherein said second stressed layer is formed on said first stressed layer.  
   
   
       29 . The method of  claim 25 , wherein at least one of said first stressed layer and said second stressed layer comprises a dielectric material.  
   
   
       30 . The method of  claim 25 , further comprising forming at least one first contact via through said first stressed layer and forming at least one second contact via through said first stressed layer and said second stressed layer, said first contact via being located above said first transistor element, said second contact via being located above said second transistor element.  
   
   
       31 . A method of forming a semiconductor structure, comprising: 
 providing a substrate comprising a first transistor element having a first channel region and a second transistor element having a second channel region;    forming a first stressed layer above said first transistor element and said second transistor element, said first stressed layer having a first predetermined intrinsic stress;    forming a liner layer on said first stressed layer;    forming a second stressed layer above said liner layer, said first stressed layer, said first transistor element and said second transistor element, said second stressed layer having a second predetermined intrinsic stress; and    selectively removing a portion of said second stressed layer located above said first transistor element.    
   
   
       32 . The method of  claim 31 , wherein said second channel region is substantially unstressed and said first channel region is stressed.  
   
   
       33 . The method of  claim 31 , wherein said first transistor element is an N-type transistor and said second transistor element is a P-type transistor.  
   
   
       34 . The method of  claim 33 , wherein said first predetermined intrinsic stress is tensile and said second predetermined intrinsic stress is compressive.  
   
   
       35 . The method of  claim 31 , wherein said second stressed layer is formed on said liner layer.  
   
   
       36 . The method of  claim 31 , wherein at least one of said first stressed layer and said second stressed layer comprises a dielectric material.  
   
   
       37 . The method of  claim 31 , further comprising forming at least one first contact via through said first stressed layer and said liner layer and forming at least one second contact via through said first stressed layer, said liner layer and said second stressed layer, said first contact via being located above said first transistor element, said second contact via being located above said second transistor element.