Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in aeries together is disclosed. A select gate translator is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate translator is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

1 . A nonvolatile semiconductor memory device, comprising: 
 a cell unit including a plurality of electrically rewritable nonvolatile memory cells connected in series;    a first dummy cell being out of use for data storage, including a pair of ends, one of the ends of the first dummy cell being connected to one end of the cell unit;    a second dummy cell being out of use for data storage, including a pair of ends, one of the ends of the second dummy cell being connected to the other end of the cell unit;    a first select gate transistor including a pair of ends, one of the ends of the first select gate transistor being connected to the other end of the first dummy cell;    a second select gate transistor including a pair of ends, one of the ends of the second select gate transistor being connected to the other end of the second dummy cell;    a bit line connected to the other end of the first select gate transistor; and    a source line connected to the other end of the second select gate transistor.    
   
   
       2 . The device according to  claim 1 , wherein a structure of the first and the second dummy cells are the same as a structure of the memory cell.  
   
   
       3 . The device according to  claim 1 , wherein each memory cell includes a floating gate and a control gate stacked on the floating gate via an insulating film.  
   
   
       4 . The device according to  claim 3 , wherein a structure of the first and the second dummy cells is the same as a structure of the memory cell.  
   
   
       5 . The device according to  claim 1 , wherein the first and the second dummy cells are applied with a bias voltage being the same as a bias voltage for the memory cells during data erase.  
   
   
       6 . The device according to  claim 1 , wherein the first and the second dummy cells are applied with a bias voltage being the same as a bias voltage of non-selected memory cells in data read and write events.  
   
   
       7 . A nonvolatile semiconductor memory device, comprising: 
 a semiconductor substrate;    a cell unit including a plurality of electrically rewritable nonvolatile memory cell transistors connected in series, each memory cell transistor including a first gate electrode having a data storage layer formed on the semiconductor substrate via a first insulator;    a first dummy transistor including a second gate electrode formed on the semiconductor substrate via a second insulator, the first dummy transistor being out of use for data storage, the first dummy transistor being electrically connected to one end of the cell unit via a first diffusion layer formed in the semiconductor substrate, the first dummy transistor being applied with a predetermined bias voltage during data erase or data write operation;    a second dummy transistor including a third gate electrode formed on the semiconductor substrate via a third insulator, the second dummy transistor being out of use for data storage, the second dummy transistor being electrically connected to the other end of the cell unit via a second diffusion layer formed in the semiconductor substrate, the second dummy transistor being applied with the predetermined bias voltage during data erase or data write operation;    a first select gate transistor including a fourth gate electrode formed on the semiconductor substrate via a fourth insulator, the first select gate transistor being electrically connected to the first dummy transistor via a third diffusion layer formed in the semiconductor substrate;    a second select gate transistor including a fifth gate electrode formed on the semiconductor substrate via a fifth insulator, the second select gate transistor being electrically connected to the second dummy transistor via a fifth diffusion layer formed in the semiconductor substrate;    a bit line electrically connected to the first select gate transistor via a sixth diffusion layer; and    a source line electrically connected to the second select gate transistor via a seventh diffusion layer.    
   
   
       8 . The device according to  claim 7 , wherein the data storage layer includes a floating gate having a polycrystalline silicon film.  
   
   
       9 . The device according to  claim 7 , wherein a structure of the first and the second dummy transistors are same as a structure of the memory cell.  
   
   
       10 . The device according to  claim 7 , wherein the first and the second dummy transistors are applied with a bias voltage being the same as a bias voltage of non-selected memory cells in data write events.