Low-power high-performance storage circuitry

Abstract

An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate coupled to a first access control node; and a second low threshold voltage access transistor including a first S/D coupled to the second data node and to the gate of the first PMOS transistor and to the gate of the first NMOS transistor and including a second S/D coupled to a second data access node and including a gate coupled to a second access control node.

1 . (canceled)  
   
   
       2 . An integrated circuit comprising: 
 a latch circuit including,    a first inverter including a first PMOS transistor and a first NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors;    a second inverter including a second PMOS transistor and a second NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors;    wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node;    wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node;    a first input switch coupled to selectably communicate input data from a first data access node to the first data node; and    a first output switch, which includes a first discharge path coupled separate from the latch circuit to selectably discharge a precharge voltage in response to a stored data value of the first data node.    
   
   
       3 . The integrated circuit of  claim 2  further including: 
 a second input switch coupled to selectably communicate input data from a second data access node to the second data node.    
   
   
       4 . The integrated circuit of  claim 2  further including: 
 a second output switch, which includes a second discharge path coupled separate from the latch circuit to selectably discharge a precharge voltage in response to a stored data value of the second data node.    
   
   
       5 . The integrated circuit of  claim 2  further including: 
 a second input switch coupled to selectably communicate input data from a second data access node to the second data node; and    a second output switch, which includes a second discharge path coupled separate from the latch circuit to selectably discharge a precharge voltage in response to a stored data value of the second data node.    
   
   
       6 . The integrated circuit of  claim 2  wherein, 
 the first input switch includes an access transistor including a first S/D coupled to the first data node and including a second S/D coupled to the first data access node and including a gate coupled to a first access control node.    
   
   
       7 . The integrated circuit of  claim 2 , 
 wherein the first output switch includes,    a first output transistor;    a second output transistor; and    wherein the first output transistor has a first S/D coupled to the first discharge path and has a second S/D coupled to a first S/D of the second output transistor and has a gate coupled to the first data node; and    wherein the second output transistor has a second source/drain coupled to a second data access node and has a gate coupled to a second access control node.    
   
   
       8 . The integrated circuit of  claim 2 , 
 wherein the first input switch includes an access transistor including a first S/D coupled to the first data node and including a second S/D coupled to the first data access node and including a gate coupled to a first access control node;    wherein the first output switch includes,    a first output transistor;    a second output transistor; and    wherein the first output transistor has a first S/D coupled to the first discharge path and has a second S/D coupled to a first S/D of the second output transistor and has a gate coupled to the first data node; and    wherein the second output transistor has a second source/drain coupled to a second data access node and has a gate coupled to a second access control node; and    wherein the second output switch that includes,    a third output transistor;    a fourth output transistor; and    wherein the third output transistor has a first S/D coupled to a second discharge path and has a second S/D coupled to a first S/D of the fourth output transistor and has a gate coupled to the second data node; and    wherein the fourth output transistor has a second source/drain coupled to the first data access node and has a gate coupled to a third access control node.    
   
   
       9 . The integrated circuit of  claim 2  further including: 
 a second input switch that includes an access transistor including a first S/D coupled to the second data node and including a second S/D coupled to a second data access node and including a gate coupled to the first access control node.    
   
   
       10 . An integrated circuit comprising: 
 a latch circuit including,    a first inverter including a first PMOS transistor and a first NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors;    a second inverter including a second PMOS transistor and a second NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors;    wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node;    wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node;    a first input switch coupled to selectably communicate input data from a first data access node to the first data node; and    a first output switch, which includes a first discharge path coupled separate from the latch circuit to selectably discharge a precharge voltage in response to a stored data value of the second data node.    
   
   
       11 . The integrated circuit of  claim 10  wherein, 
 the first input switch includes an access transistor including a first S/D coupled to the first data node and including a second S/D coupled to the first data access node and including a gate coupled to a first access control node.    
   
   
       12 . The integrated circuit of  claim 10 , 
 wherein the first output switch includes,    a first output transistor;    a second output transistor; and    wherein the first output transistor has a first S/D coupled to the first discharge path and has a second S/D coupled to a first S/D of the second output transistor and has a gate coupled to the second data node; and    wherein the second output transistor has a second source/drain coupled to the first data access node and has a gate coupled to a second access control node.    
   
   
       13 . The integrated circuit of  claim 10 , 
 wherein the first input switch includes an access transistor including a first S/D coupled to the first data node and including a second S/D coupled to the first data access node and including a gate coupled to a first access control node;    wherein the first output switch includes,    a first output transistor;    a second output transistor; and    wherein the first output transistor has a first S/D coupled to the first discharge path and has a second S/D coupled to a first S/D of the second output transistor and has a gate coupled to the second data node; and    wherein the second output transistor has a second source/drain coupled to the first data access node and has a gate coupled to a second access control node.