Wireless communication semiconductor integrated circuit device and wireless communication system

Abstract

A receiving circuit of a direct conversion system which includes a differential amplifier circuit which amplifies a received signal, a mixer which combines the amplified received signal and an oscillation signal having a predetermined frequency to perform frequency conversion, and a high gain amplifier circuit in which programmable gain amplifiers and filters which eliminate noise of the received signal, are connected in a multistage and which is configured such that an amplification factor is varied according to the level of the received signal. In the receiving circuit, the low noise amplifier is brought to a non-operating state to allow execution of a DC offset cancel operation of the programmable gain amplifier on the pre-stage side of the high gain amplifier circuit. Thereafter, the low noise amplifier is brought to an operating state to allow execution of a DC offset cancel operation of the final-stage programmable gain amplifier.

1 . A wireless communication system comprising: 
 an antenna which transmits and receives a signal wave;    transmit-receive switching means which supplies a transmission signal output from a transmission circuit to an antenna and supplies a reception signal received at the antenna to a reception circuit;    single differential converters which converts the reception signal from the transmit-receive switching means into a differential signal; and    a baseband circuit which performs baseband processing on the transmission signal and reception signal,    wherein the reception circuit including:    a low noise amplifier circuit which amplifies the differential signal,    a mixer which synthesize an output of the low noise amplifier circuit and an oscillation signal having a predetermined frequency, and    a high gain amplifier circuit which includes a plurality of programmable gain amplifiers and a plurality of filters are alternately connected in series,    wherein the low noise amplifier circuit is brought to a non-operating state to allow execution of an offset cancel operation of the programmable gain amplifier on the pre-stage side of the high gain amplifier circuit, and thereafter the low noise amplifier circuit is brought to an operating state to allow execution of an offset cancel operation of the programmable gain amplifier corresponding to a final stage,    wherein reception circuit further comprising:    a register or control bit capable of setting whether or not the offset cancel operation for the pre-stage side of the programmable gain amplifier and the offset cancel operation for the final stage of the programmable gain amplifier, and    wherein a value set to the register or the control bit is supplied from the baseband circuit to the reception circuit.    
   
   
       2 . A wireless communication system according to  claim 1 , wherein the reception circuit further comprising: 
 an offset cancel circuit which includes offset collection circuits provided in association with the programmable gain amplifiers and a control circuit which receives the value from the baseband circuit and controls the offset collection circuits,    wherein the register or the control bit are included in the control circuit.    
   
   
       3 . A wireless communication system according to  claim 2 , wherein the transmission circuit and the reception circuit are formed on a high frequency integrated circuit device, and 
 wherein the baseband circuit and the high frequency integrated circuit device are respectively formed on a semiconductor integrated circuit device.    
   
   
       4 . A wireless communication system according to  claim 2 , wherein the threshold value for determining which one of the two offset cancel operations is executed, is a fixed value.  
   
   
       5 . A wireless communication system according to  claim 4 , wherein the first gain is higher than the second gain.