US2007201277A1PendingUtilityA1

NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Mar 22, 2005Filed: Apr 25, 2007Published: Aug 30, 2007
Est. expiryMar 22, 2025(expired)· nominal 20-yr term from priority
C02F 3/20G11C 16/26B01F 23/237612B01F 23/2312
57
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

Claims

exact text as granted — not AI-modified
1 . A method of sequentially sensing multiple data bits stored in a multilevel cell of a NOR flash memory device, the method comprising: 
 initializing a data line and sensing a higher data bit;    loading the sensed higher data bit on the data line and latching the loaded higher data bit;    initializing the data line and sensing a lower data bit in response to the latched higher data bit; and    loading the sensed lower data bit on the data line and latching the loaded lower data bit.    
   
   
       2 . The method as set forth in  claim 1 , wherein the data line is initialized before sensing the higher data bit.  
   
   
       3 . The method as set forth in  claim 2 , wherein the data line is initialized before sensing the lower data bit.  
   
   
       4 . The method as set forth in  claim 1 , wherein the data line is initialized while sensing the higher data bit.  
   
   
       5 . The method as set forth in  claim 4 , wherein the data line is initialized when beginning to sense the higher data bit.  
   
   
       6 . The method as set forth in  claim 4 , wherein the data line is initialized while sensing the lower data bit.  
   
   
       7 . The method as set forth in  claim 6 , wherein the data line is initialized when beginning to sense the lower data bit.

Join the waitlist — get patent alerts

Track US2007201277A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.