Squelch detecting circuit

Abstract

The present invention provides a squelch detecting circuit capable of high-speed transfer while using a reduced number of high-speed operating operational amplifiers to reduce power consumption and the cost of parts. Input differential signals inputted to a differential amplification circuit are amplified and the amplified signal is outputted to a gain proportion circuit. The gain proportion circuit supplies a potential holding circuit with a potential proportional to the amplified signal. The potential holding circuit holds the potential supplied from the gain proportion circuit. A comparator circuit compares the potential held by the potential holding circuit with a reference potential to decide whether it is a squelch state or a non-squelch state and outputs the result as a detect signal.

1 - 10 . (canceled)  
   
   
       11 . A serial interface comprising: 
 a first input terminal;    a second input terminal; and    a squelch detecting circuit, wherein    said squelch detecting circuit comprises 
 a differential amplification circuit that amplifies differential input signals from said first and second input terminals to output an amplified signal,  
 a gain proportion circuit that supplies a potential proportional to said amplified signal,  
 a potential holding circuit that holds said potential supplied from said gain proportion circuit, and  
 a comparator circuit that compares said potential held by said potential holding circuit and a reference potential to output a detect signal.  
   
   
   
       12 . The serial interface according to claim  1 , wherein said interface is used for the USB2.0.  
   
   
       13 . The serial interface according to claim  1 , wherein said interface is used for the Serial ATA.  
   
   
       14 . The serial interface according to claim  1 , wherein said gain proportion circuit comprises an n-channel transistor that receives said amplified signal at its control electrode and supplies a potential to said potential holding circuit, and wherein said potential holding circuit comprises a first current source having its one terminal connected to GND, and a first capacitance having its one terminal connected to said first electrode of said n-channel transistor and having the other terminal connected to GND.  
   
   
       15 . The serial interface according to claim  1 , wherein said gain proportion circuit comprises a p-channel transistor that receives said amplified signal at its control electrode and supplies a potential to said potential holding circuit, and wherein said potential holding circuit comprises a first current source having its one terminal connected to a first electrode of said p-channel transistor and other terminal connected to a power supply, and a first capacitance having its one terminal connected to said first electrode of said p-channel transistor and having the other terminal connected to said power supply.