Semiconductor device with strained transistors and its manufacture

Abstract

A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.

1 . A semiconductor device comprising: 
 a semiconductor substrate made of a first semiconductor material;    an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and    a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein said n-type source/drain regions and said p-type source/drain regions are made of single-crystal.  
     
     
         3 . The semiconductor device according to  claim 2 , wherein said second semiconductor material has a lattice constant smaller than a lattice constant of said first semiconductor material.  
     
     
         4 . The semiconductor device according to  claim 2 , wherein said third semiconductor material has a lattice constant larger than a lattice constant of said first semiconductor material.  
     
     
         5 . The semiconductor device according to  claim 1 , wherein said first semiconductor material is Si, said second semiconductor material contains Si and C, and said third semiconductor material contains Si ang Ge.  
     
     
         6 . The semiconductor device according to  claim 5 , wherein a C composition of said second sedmiconductor material is 0.1 to 5.0 at %.  
     
     
         7 . The semiconductor device according to  claim 5 , wherein a Ge composition of said third semiconductor material is 5 to 40 at %.  
     
     
         8 . The semiconductor device according to  claim 5 , wherein: 
 said n-channel field effect transistor and said p-channel field effect transistor each have a gate electrode formed above said semiconductor substrate and sidewall spacers of insulator formed on side walls of the gate electrode;    said n-type source/drain regions have an uneven upper surface, and bottom of the sidewall spacer of said n-channel field effect transistor has at least partially uneven surface in conformity with the upper surface of said n-type source/drain region; and    the sidewall spacer of said p-type field effect transistor has a flat bottom.    
     
     
         9 . A method of manufacturing a semiconductor device comprising the steps of: 
 (1) forming gate electrodes above an n-channel field effect transistor region and a p-channel field effect transistor region of a semiconductor substrate made of a first semiconductor material;    (2) forming a first insulating mask layer on the semiconductor substrate, covering the gate electrodes;    (3) covering one of the n-channel field effect transistor region and the p-type field effect transistor region with a resist mask, anisotropically etching the first insulating mask layer in the other field effect transistor region to leave the first insulating mask layer of a sidewall spacer shape on sidewalls of the gate electrode of the other field effect transistor;    (4) etching the semiconductor substrate in the other field effect transistor region by using the first insulating mask layer as an etching mask, to form first recesses;    (5) epitaxially growing source/drain regions of a second semiconductor material different from the first semiconductor material, on the first recesses;    (6) removing the first insulating mask layer;    (7) forming sidewall spacers of an insulating material on sidewalls of the gate electrodes;    (8) forming a second insulating mask layer covering the other field effect transistor region;    (9) etching the semiconductor substrate in the one field effect transistor region by using the second insulating mask layer and the sidewall spacers, as an etching mask, to form second recesses; and    (10) epitaxially growing source/drain regions of a third semiconductor material different from the first semiconductor material, on the second recesses.    
     
     
         10 . The method of manufacturing a semiconductor device according to  claim 9 , wherein at least one of said steps (4) and (9) includes an anisotropical etching process and an isotropical etching process following the anisotropical etching process.  
     
     
         11 . The method of manufacturing a semiconductor device according to  claim 9 , further comprising between said steps (6) and (8) a step of implanting impurity ions into said one and other field effect transistor regions.  
     
     
         12 . The method of manufacturing a semiconductor device according to  claim 9 , wherein said step (5) epitaxially grows semiconductor containing Si and C at a first temperature, and said step (10) epitaxially grows semiconductor containing Si and Ge at a second temperature lower than said first temperature.  
     
     
         13 . The method of manufacturing a semiconductor device according to  claim 9 , wherein said first semiconductor is Si, said second semiconductor is Si-C mixed crystal, and said third semiconductor is Si-Ge or Si-Ge-C mixed crystal.  
     
     
         14 . The method of manufacturing a semiconductor device according to  claim 13 , wherein each of said steps (4) and (9) includes (a) a reactive etching step for Si and (b) a chemical etching process for Si.  
     
     
         15 . The method of manufacturing a semiconductor device according to  claim 14 , wherein said step (a) etches a depth of 20 to 100 nm and said step (b) etched a depth of 5 to 40 nm.  
     
     
         16 . The method of manufacturing a semiconductor device according to  claim 14 , wherein said step (a) uses HBr as etchant.  
     
     
         17 . The method of manufacturing a semiconductor device according to  claim 14 , wherein said step (b) etches at 600 to 900° C. using HCl or Cl 2  as etchant.  
     
     
         18 . The method of manufacturing a semiconductor device according to  claim 13 , wherein said step (5) is performed by low pressure thermal CVD using silane gas as Si source gas and SiH 3 (CH 3 ) as C source gas.  
     
     
         19 . The method of manufacturing a semiconductor device according to  claim 13 , wherein said step (10) is performed by low pressure thermal CVD using silane gas as Si source gas and GeH 4  as Ge source gas.  
     
     
         20 . The method of manufacturing a semiconductor device according to  claim 9 , wherein said step (7) includes a step of depositing a silicon oxide film by thermal CVD using BTBAS and O2 as source gasses.