US2007194420A1PendingUtilityA1

Semiconductor package having an optical device and a method of making the same

Assignee: FENG YAO-HSINPriority: Mar 1, 2005Filed: Apr 24, 2007Published: Aug 23, 2007
Est. expiryMar 1, 2025(expired)· nominal 20-yr term from priority
Inventors:Yao-Hsin Feng
H10W 72/0198H10W 72/29H10W 70/65H10W 70/05H10W 70/093H10W 72/01331H10W 72/252H10W 72/242H10W 72/244H10W 72/01225H10P 54/00H10W 72/90H10W 72/019H10W 20/49H10W 74/129H10W 74/111
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Claims

Abstract

A semiconductor package having an optical device and a method of making the same, the package including a chip, an upper metal redistribution layer, a transparent insulating layer, and a lower metal redistribution layer. The chip has an active surface, a back surface, at least one through hole, an optical device, and at least one upper pad. The optical device is electrically connected to the upper pad. The through hole is filled with a metal post. An insulating layer is between the through hole wall and the metal post. The upper metal redistribution layer is on the chip active surface, and connects the upper pad and the metal post. The transparent insulating layer is on the active surface. The lower metal redistribution layer is on the back surface of the chip, and is connected to the metal post. A simplified manufacturing process having reduced cost is provided.

Claims

exact text as granted — not AI-modified
1 . A semiconductor package having an optical device, comprising: 
 a chip, having an active surface, a back surface, and at least one through hole, wherein the active surface has at least one upper pad and an optical device electrically connected to the upper pad, and the through hole is filled with a metal post, and an insulating layer is disposed between the wall of the through hole and the metal post;    an upper metal redistribution layer, disposed on the active surface of the chip, wherein the upper metal redistribution layer connects the upper pad and the metal post;    a transparent insulating layer, disposed on the active surface of the wafer; and    a lower metal redistribution layer, disposed on the back surface of the wafer, the lower metal redistribution layer being electrically connected to the metal post.    
     
     
         2 . The package according to  claim 1 , further comprising a dielectric layer disposed between the upper metal redistribution layer and the active surface of the wafer.  
     
     
         3 . The package according to  claim 1 , further comprising a compliance layer disposed between the back surface of the wafer and the lower metal redistribution layer.  
     
     
         4 . The package according to  claim 1 , further comprising a solder mask disposed on the lower surface of the lower metal redistribution layer.  
     
     
         5 . The package according to  claim 4 , wherein the solder mask has at least one opening by which a lower pad of the lower metal redistribution layer is defined.  
     
     
         6 . The package according to  claim 5 , further comprising a plurality of solder balls disposed on the lower pad.  
     
     
         7 . The package according to  claim 1 , further comprising a plurality of solder balls disposed on the lower metal redistribution layer.

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