Data processing system

Abstract

It is an object to obtain a self-synchronization type block processing apparatus which does not need to optimize a clock path to be distributed to each block in a clock phase management at an upper level, and can suppress an increase in a circuit scale and can minimize an increase in a design period by circuit tuning. A local block control circuit comprises an end detecting section for receiving a plurality of complete signals, a transfer control section for generating a stop signal having a negative logic to determine whether or not a system clock is supplied to a processing block upon receipt of an end signal output from the end detecting section, the system clock and a handshaking control signal, and a logical AND gate for generating an in-block clock based on the stop signal having the negative logic which is output from the transfer control section and the system clock.

1 . A data processing system for processing data via a plurality of processing blocks, comprising: 
 a plurality of block control circuits provided corresponding to said respective processing blocks,    said block control circuits controlling corresponding processing blocks by a clock synchronization respectively and transferring a handshaking control signal with other block control circuits, thereby controlling a data transfer between said processing blocks by self-synchronization type handshaking,    wherein said data processing system further includes an arbitration circuit for interfacing with an external system,    said arbitration circuit transferring a system control signal synchronous with a clock with said external system, thereby creating said handshaking control signal based on said system control signal.