Transistors of Semiconductor Devices and Methods of Fabricating the Same

Abstract

Transistors and methods of fabricating transistors are disclosed. A disclosed method comprises forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; depositing a silicon epitaxial layer over the inversion epitaxial layer; forming a trench through the silicon epitaxial layer by removing the hard mask; forming reverse spacers on the sidewalls of the trench by filling the trench with an insulating layer and etching the insulating layer; forming a gate electrode over the reverse spacers; forming pocket-well regions and LDD regions in the silicon substrate by performing ion implantations; forming spacers on the sidewalls of the gate electrode; forming source and drain regions in the silicon substrate by performing an ion implantation; and forming a silicide layer on the gate electrode and the source and drain regions.

1 . A method of fabricating a transistor, comprising: 
 forming an inversion epitaxial layer on a silicon substrate;    forming a hard mask on the inversion epitaxial layer;    forming a silicon epitaxial layer over the inversion epitaxial layer; and    forming a trench through the silicon epitaxial layer by removing the hard mask.    
   
   
       2 . The method as defined by  claim 1 , further comprising: 
 filling the trench with an insulating layer; and    forming reverse spacers on sidewalls of the trench by etching the insulating layer.    
   
   
       3 . The method as defined by  claim 2 , wherein the reverse spacers are formed by a dry etching process.  
   
   
       4 . The method as defined by  claim 2 , wherein the reverse spacers are formed of a single layer of TEOS or a multi-layer of TEOS-SiN-TEOS.  
   
   
       5 . The method as defined by  claim 2 , further comprising: 
 forming a gate electrode over the reverse spacers, the gate electrode being positioned above the inversion epitaxial layer between the reverse spacers; and    performing ion implantation using the gate electrode as a mask to form pocket-well regions and LDD regions.    
   
   
       6 . The method as defined by  claim 5 , further comprising: 
 forming spacers on sidewalls of the gate electrode;    forming source/drain regions by performing ion implantation using the gate electrode and the spacers as a mask; and    forming a silicide layer on the gate electrode and the source and drain regions.    
   
   
       7 . The method as defined by  claim 6 , wherein the source and drain regions are elevated source and drain regions.  
   
   
       8 . The method as defined by  claim 6 , wherein the silicide layer on the source and drain regions is formed through the silicon epitaxial layer on the source and drain regions.  
   
   
       9 . The method as defined by  claim 6 , wherein the inversion epitaxial layer is used as an SSR epitaxial channel.  
   
   
       10 . The method as defined by  claim 6 , wherein a gate channel is located under the gate electrode, the gate channel having a length defined by a length of the inversion epitaxial layer exposed between the reverse spacers.  
   
   
       11 . The method as defined by  claim 6 , wherein the gate electrode has a width smaller than the trench and larger than a space between the reverse spacers.