Nonvolatile semiconductor memory device and manufacturing method therefor

Abstract

A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit and also including forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate.

1 . A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit, comprising: 
 forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate;    forming a tunnel insulating film and a gate insulating film on a substrate surface including the first and second wells;    depositing a first polysilicon film on the substrate surface;    covering the first well with a resist mask to carry out ion implantation into the second well, thereby forming a channel region therein;    after removing the resist mask from the first well, depositing a second polysilicon film on the first polysilicon film;    forming a silicon nitride film on the second polysilicon film;    forming on the silicon nitride film a resist pattern having openings for isolation regions;    sequentially selectively removing the film structure from the silicon nitride film to the first and second wells by using the resist pattern to provide isolation trenches in the first and second wells;    after removing the resist pattern, burying an oxide film in the isolation trenches;    after planarizing the substrate surface, removing the silicon nitride film;    forming an ONO stacked film on the substrate surface;    forming a resist mask on the first well to selectively remove the ONO stacked film from the second well;    depositing at least a conductive film on the substrate surface;    sequentially selectively removing the conductive film, the ONO stacked film, the second polysilicon film, and the first polysilicon film to expose the tunnel insulting film on the first well and the gate oxide film on the second well; and    introducing an impurity into the first and second wells to provide source and drain regions.    
   
   
       2 . The method according to  claim 1 , wherein a floating gate of the memory cell and a gate of the MOS transistor are self-aligned at an isolation end in a direction of a channel width by forming the isolation trenches in the first and second wells.  
   
   
       3 . The method according to  claim 1 , wherein the tunnel insulting film is heat-treated in an NH 3  atmosphere to introduce nitrogen thereinto.  
   
   
       4 . The method according to  claim 1 , wherein the tunnel insulting film is annealed in an oxygen atmosphere to provide an oxynitride tunnel insulating film.  
   
   
       5 . The method according to  claim 1 , wherein the first polysilicon film includes an undoped polysilicon film.  
   
   
       6 . The method according to  claim 1 , wherein the first polysilicon film includes a doped polysilicon film.  
   
   
       7 . The method according to  claim 1 , wherein the second polysilicon film includes a doped polysilicon film.  
   
   
       8 . The method according to  claim 1 , wherein an oxide film is provided between the first polysilicon film and the second polysilicon film.  
   
   
       9 . The method according to  claim 1 , wherein the second polysilicon film includes an undoped polysilicon film, and an impurity is introduced later.  
   
   
       10 . The method according to  claim 1 , wherein the step of depositing at least the conductive film on the substrate surface comprises sequentially depositing a doped polysilicon film, a tungsten silicide film, and a silicon nitride film on the substrate surface.  
   
   
       11 . A method of manufacturing a nonvolatile semiconductor memory device, comprising: 
 forming a well in a semiconductor substrate in a memory cell area;    forming a tunnel insulating film on the semiconductor substrate in which the well is formed;    forming a first conductive film on the tunnel insulating film;    selectively implanting an ion in the well through the first conductive film and the tunnel insulating film so as to form a channel region in the well;    forming a second conductive film on the first conductive film;    sequentially selectively etching the first and the second conductive films, the tunnel insulating film and the well so as to form a isolation trench;    embedding a silicon oxide film in the isolation trench;    forming an inter-gate insulator on the second conductive film and the silicon oxide film;    forming a third conductive film on the inter-gate insulator;    sequentially selectively etching the third conductive film, the inter-gate insulator, the first and the second conductive film and the tunnel insulating film so as to form a gate electrode of a memory cell;    forming a source and a drain areas of the memory cell in the well.    
   
   
       12 . The method according to  claim 11 , wherein the tunnel insulating film includes an oxynitride film which contains nitrogen in a tunnel oxide film.  
   
   
       13 . The method according to  claim 11 , wherein the tunnel insulating film is formed by annealing the semiconductor substrate in an oxygen atmosphere to form a tunnel oxide film and treating the tunnel oxide film in a NH 3  atmosphere to introduce a nitrogen therein.  
   
   
       14 . The method according to  claim 11 , wherein the first conductive film includes an undoped polysilicon film, and the second conductive film includes a phosphorous-doped polysilicon film.  
   
   
       15 . The method according to  claim 11 , wherein the ion includes boron.  
   
   
       16 . The method according to  claim 11 , wherein the third conductive film includes a polysilicon film and a tungsten silicide film.  
   
   
       17 . The method according to  claim 11 , wherein the inter-gate insulator includes an ONO film.