Fast read port for register file

Abstract

Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier provides a mid-supply-level precharging capability provided by a feedback device within a front-end inversion stage. When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage provides a rapid read response.

1 . A memory system comprising: 
 a memory cell array, the memory cell array being a matrix of memory cells organized by rows and columns, each of the memory cells accessible by a pair of write ports and a read port, each column of the memory cells being commonly coupled by a bitline pair and a read bitline;    a row decoder, the row decoder coupled to each of the pairs of write ports and each of the read ports, the row decoder configured to receive a storage location address and couple a subset of the pairs of write ports and a subset of the read ports to respective bitline pairs and respective read bitlines corresponding to the storage location address;    a column decoder, the column decoder coupled to each of the pairs of write ports in the memory cell array and configured to access a subset of the pairs of write ports in a single column of memory cells at a time in a memory cell write operation;    a read bitline multiplexer, the read bitline multiplexer coupled to the read ports of the memory cell array and configured to select a subset of the read ports corresponding to a single column of memory cells at a time in a memory cell read operation;    a sense amplifier, the sense amplifier coupled to the read bitline multiplexer and configured to read a data content from a selected memory cell, the sense amplifier further configured to precharge a single one of the read bitlines at a time in a read operation; and a control block, the control block coupled to the row decoder, the column decoder, the read bitline multiplexer, and the sense amplifier and configured to produce control signals in read and write operations.