Package on package design a combination of laminate and tape substrate, with back-to-back die combination

Abstract

In a method and system for fabricating a semiconductor device ( 100 ) having a package-on-package structure, a bottom laminate substrate (BLS) ( 130 ) is formed to include interconnection patterns (IP) ( 170, 172 ) coupled to a plurality of conductive bumps (PCB) ( 130 ). A top substrate (TS) ( 140 ) is formed to mount a top package ( 110 ) by forming a polyimide tape (PT) ( 142 ) affixed to a metal layer (ML) ( 144 ), and a top die ( 136 ) attached to the ML ( 144 ) on an opposite side as the PT ( 142 ). A laminate window frame (LWF) ( 150 ), which may be a part of the BLS ( 130 ), is fabricated along a periphery of the BLS ( 130 ) to form a center cavity ( 160 ). The center cavity ( 160 ) enclosed by the BLS, the LWF and the TS houses the top die ( 136 ) affixed back-to-back to a bottom die ( 134 ) that is affixed to the BLS ( 130 ). The IP ( 170, 172 ) formed in the BLS and the LWS ( 150 ) provide the electrical coupling between the ML ( 144 ), the top and bottom dies ( 136, 134 ), and the PCB ( 130 ).

1 . A semiconductor device comprising:
 a bottom laminate substrate having a laminate window frame portion, wherein the laminate window frame portion is disposed along a periphery of the bottom laminate substrate;   a top substrate to mount a top package, the top package having a full matrix footprint, wherein the top substrate includes a polyimide tape affixed to a metal layer, and a top die attached to the metal layer on an opposite side as the polyimide tape;   a center cavity enclosed between the bottom laminate substrate, the laminate window frame and the top substrate to house the top die affixed back-to-back to a bottom die, the bottom die being affixed to the bottom laminate substrate; and   interconnection patterns included in the bottom laminate substrate, the laminate window frame and the center cavity, wherein the interconnection patterns provide electrical coupling between the metal layer, the top die, the bottom die, and a plurality of conductive bumps disposed on a bottom surface of the bottom laminate substrate.   
   
   
       2 . The device of  claim 1 , wherein the top substrate includes:
 a plurality of holes formed in the polyimide tape, the plurality of holes being arranged in a full matrix array pattern to match the full matrix footprint; and   a plurality of metal lands of the metal layer, wherein each one of the plurality of holes exposes a corresponding one of the plurality of metal lands, wherein the top package having the full matrix footprint is mounted on the plurality of metals lands.   
   
   
       3 . The device of  claim 2 , wherein the plurality of holes reduces a profile of the top package by providing a recess for a contact element of the full matrix footprint. 
   
   
       4 . The device of  claim 2 , wherein each one of the plurality of holes formed in the polyimide tape includes a wall surface, wherein the wall surface in contact with an edge of a contact element of the full matrix footprint provides support for the top package. 
   
   
       5 . The device of  claim 1 , wherein the metal layer is bonded to the interconnection patterns included in the laminate window frame by one of a conductive adhesive, a thermo compression weld, and a high melting point solder contact. 
   
   
       6 . The device of  claim 1 , wherein the top die is affixed back-to-back to a bottom die by a die attach compound. 
   
   
       7 . The device of  claim 1 , wherein the interconnection patterns in the bottom laminate substrate, the laminate window frame and the center cavity include a plurality of conductive traces, vias, metal planes, bond wires, metal lands, conductive pads, a conductive adhesive, a thermo compression weld, and a high melting point solder contact. 
   
   
       8 . The device of  claim 1 , wherein the top die and the bottom die is one of a microprocessor, a digital signal processor, a radio frequency chip, a memory, a microcontroller, and a system-on-a-chip or a combination thereof. 
   
   
       9 . The device of  claim 1 , wherein the full matrix footprint includes contact elements arranged in a two dimensional matrix array on a bottom surface of the top package, wherein an arrangement of the contact elements is free from space restrictions. 
   
   
       10 . The device of  claim 1 , wherein the device is less than 1.4 millimeters thick. 
   
   
       11 . The device of  claim 1 , further comprising:
 a bottom package, wherein the bottom package includes the bottom laminate substrate without the laminate window frame portion, the top substrate, the laminate window frame, and the center cavity, wherein the laminate window frame is disposed along the periphery of the bottom laminate substrate but is separate from the bottom laminate substrate.   
   
   
       12 . The device of  claim 1 , wherein a height of the bottom package inclding the conductive bumps is less than 0.6 millimeters. 
   
   
       13 . The device of  claim 1 , wherein a body size of the top package resembles a rectangle, wherein the rectangle has linear dimensions varying approximately between 5 millimeters and 20 millimeters. 
   
   
       14 . A method for fabricating a semiconductor device having a package-on-package structure, the method comprising:
 assembling a bottom laminate substrate having a laminate window frame portion, wherein forming the bottom laminate substrate includes forming the laminate window frame disposed along a periphery of the bottom laminate substrate to form a center cavity, wherein forming the bottom laminate substrate and the laminate window frame includes forming interconnection patterns to provide electrical coupling;   attaching a bottom die to the bottom laminate substrate within the center cavity;   assembling a top substrate to mount a top package, wherein the top substrate includes a top die attached to a metal layer, the metal layer being affixed to a polyimide tape, wherein the top die is affixed to the metal layer on an opposite side as the polyimide tape;   inverting the top substrate to enable affixing the top die and the bottom die back-to-back; and   connecting the top substrate and the laminate window frame to affix the top die and the bottom die back-to-back, the top substrate and the laminate window frame being connected by the interconnection patterns, thereby enabling electrical coupling between the metal layer, the top die, the bottom die, and a plurality of conductive bumps disposed on a bottom surface of the bottom laminate substrate.   
   
   
       15 . The method of  claim 14 , wherein the assembling of the top substrate includes:
 forming a plurality of holes in the polyimide tape to expose a plurality of metal lands of the metal layer, wherein the plurality of metal lands are arranged in a full matrix array to match the full matrix footprint.   
   
   
       16 . The method of  claim 15  further comprising:
 mounting the top package on the top substrate, wherein the top package has a full matrix input output (I/O) connection footprint to match the plurality of metals lands to enable the electrical coupling.   
   
   
       17 . The method of  claim 14 , wherein the top die is one of one of a microprocessor, a digital signal processor, a radio frequency chip, a memory, a microcontroller, and a system-on-a-chip or a combination thereof. 
   
   
       18 . The method of  claim 14 , wherein the interconnection patterns include a plurality of conductive traces, vias, metal planes, bond wires, metal lands, conductive pads, a conductive adhesive, a thermo compression weld, and a high melting point solder contact. 
   
   
       19 . The method of  claim 14 , wherein the device is less than 1.4 millimeters thick. 
   
   
       20 . The method of  claim 14 , wherein the bottom die is one of one of a microprocessor, a digital signal processor, a radio frequency chip, a memory, a microcontroller, and a system-on-a-chip or a combination thereof.