Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure

Abstract

An integrated semiconductor structure includes an n-channel transistor at a surface of a semiconductor body. The n-channel transistor includes a polysilicon gate overlying a first gate dielectric. A p-channel transistor is also formed at the surface of the semiconductor body. The p-channel transistor includes an n-doped polysilicon gate overlying a second gate dielectric. The second gate dielectric includes an aluminum oxide layer between an underlying dielectric layer and the n-doped polysilicon gate.

1 . A method of manufacturing an integrated semiconductor structure, the method comprising: 
 forming a first transistor at a surface of a semiconductor body, the first transistor comprising a gate overlying a first gate dielectric, the first gate dielectric not including aluminum oxide; and    forming a second transistor at the surface of the semiconductor body, the second transistor being a different conductivity type than the first transistor, the second transistor comprising a polysilicon gate overlying a second gate dielectric, the second gate dielectric comprising an aluminum oxide layer between an underlying dielectric layer and the polysilicon gate.    
   
   
       2 . The method of  claim 1 , wherein the first transistor comprises an n-channel transistor and the second transistor comprises a p-channel transistor.  
   
   
       3 . The method of  claim 2 , wherein the first gate dielectric comprises silicon oxide and wherein the underlying dielectric layer of the second gate dielectric comprises silicon oxide.  
   
   
       4 . The method of claim.  3 , wherein the first gate dielectric layer comprises SiO 2  and wherein tie second gate dielectric layer comprises Al 2 O 3  overlying SiO 2 .  
   
   
       5 . (canceled)  
   
   
       6 . The method of  claim 2 , wherein the aluminum oxide layer comprises an Al 2 O 3  interfacial dielectric layer located adjacent to the n-doped polysilicon gate that causes a Fermi-pinning effect.  
   
   
       7 - 9 . (canceled)  
   
   
       10 . The method of  claim 1 , wherein forming the second transistor comprises depositing polysilicon and then performing a full silicidation that leaves an interface polysilicon layer.  
   
   
       11 . The method of  claim 2 , wherein forming the p-channel transistor comprises depositing silane on the aluminum oxide layer to form a polysilicon interface.  
   
   
       12 . The method of  claim 11 , further comprising depositing a metal gate layer over the polysilicon interface.  
   
   
       13 . The method of  claim 12 , wherein the metal gate layer comprises tungsten and/or TiN.  
   
   
       14 . The method of  claim 2 , wherein forming the first transistor and forming the second transistor comprise: 
 forming a first dielectric layer over the semiconductor body;    forming a second dielectric layer over the first dielectric layer; and    removing the second dielectric layer from location where the n-channel transistor will be formed.    
   
   
       15 - 16 . (canceled)  
   
   
       17 . The method of  claim 1 , wherein forming the first transistor and forming the second transistor comprise: 
 forming a first dielectric layer over the semiconductor body; and    implanting Al ions into a portion of the first dielectric layer to form the aluminum oxide over the underlying dielectric layer.    
   
   
       18 . The method of  claim 1 , wherein the semiconductor body includes a first region, a second region and a third region, the first transistor being formed in the first region, the second transistor being formed in the second region and a memory array memory array transistor being formed in the third region.  
   
   
       19 . The method of  claim 18 , wherein at least one dielectric layer is formed simultaneously in all of said first, second and third regions.  
   
   
       20 . The method of  claim 19 , wherein at least one high-k dielectric layer is formed simultaneously in all of said first, second and third regions.  
   
   
       21 . The method of  claim 20 , wherein the high-k dielectric layer comprises HfO or HfSiO or HFSiON.  
   
   
       22 . The method of  claim 18 , wherein the memory array transistor comprises a recessed channel array transistor.  
   
   
       23 . (canceled)  
   
   
       24 . The method of  claim 1 , wherein the aluminum oxide layer is made of Al x O y  or Al 2 O 3  or HfAl x O y  or any material in combination with Al 2 O 3  that forms the aluminum oxide layer.  
   
   
       25 . An integrated semiconductor structure, comprising: 
 an n-channel transistor at a surface of a semiconductor body, the n-channel transistor comprising a polysilicon gate overlying a first gate dielectric; and    a p-channel transistor at the surface of the semiconductor body, the p-channel transistor comprising an n-doped polysilicon gate overlying a second gate dielectric, the second gate dielectric comprising an aluminum oxide layer between an underlying dielectric layer and the n-doped polysilicon gate.    
   
   
       26 . The integrated semiconductor structure according to  claim 25 , wherein the aluminum oxide is in physical contact with both the underlying dielecric layer and the n-doped polysilicon gate.  
   
   
       27 . The integrated semiconductor structure according to  claim 25 , wherein aluminum oxide layer comprises Al 2 O 3 .  
   
   
       28 . The integrated semiconductor structure according to  claim 25 , wherein the aluminum oxide layer is thinner than both the underlying dielectric layer and the n-doped polysilicon gate.  
   
   
       29 . The integrated semiconductor structure according to  claim 25 , wherein the underlying dielectric layer comprises an oxide layer.  
   
   
       30 . The integrated semiconductor structure according to  claim 29 , wherein the underlying dielectric layer comprises a silicon oxide layer.  
   
   
       31 . A semiconductor device, comprising: 
 a substrate;    a gate stack comprising an oxide dielectric and an electrode overlying the substrate; and    a high-k dielectric layer containing aluminum oxide disposed between the oxide dielectric layer and the electrode.    
   
   
       32 . The semiconductor device according to  claim 31 , wherein the high-k dielectric layer containing aluminum oxide is formed in physical contact with the substrate, and wherein the electrode is formed in physical contact with the high-k dielectric layer containing aluminum oxide.  
   
   
       33 . The semiconductor device according to  claim 32 , wherein the high-k dielectric layer contains Al 2 O 3 .  
   
   
       34 . The semiconductor device according to  claim 32 , wherein the electrode comprises polysilicon.  
   
   
       35 . The semiconductor device according to  claim 31 , wherein the high-k dielectric layer is thinner than the dielectric layer and the electrode.  
   
   
       36 . A method of fabricating a semiconductor device, the method comprising: 
 providing a substrate with a first region and a second region;    forming a first dielectric layer over the substrate;    forming a second dielectric layer on the first dielectric layer, the second dielectric layer comprising an aluminum compound;    forming a mask layer over the first region and the second region;    removing the mask layer from over the first region thereby exposing the second dielectric over the first region;    removing the exposed second dielectric layer from over the first region;    removing the mask from over the second region; and    depositing a conductive material over the first and the second region.    
   
   
       37 . The method according to  claim 36 , wherein the second dielectric layer is thinner than the first dielectric layer and the conductive material.  
   
   
       38 . The method according to  claim 36 , wherein aluminum compound comprises aluminum oxide.  
   
   
       39 . The method according to  claim 38 , wherein aluminum compound comprises Al 2 O 3 .  
   
   
       40 . The method according to  claim 36 , further comprising heating the substrate after depositing the second dielectric layer.  
   
   
       41 . The method according to  claim 36 , wherein the conductive material comprises N +  doped polysilicon.  
   
   
       42 . A method of fabricating a semiconductor devices the method comprising: 
 providing a substrate with a first region and a second region;    forming a dielectric layer over the substrate;    forming a conductive material on the dielectric layer;    doping the dielectric layer over the second-region with Al ions; and    subjecting the device to a thermal treatment after the doping.    
   
   
       43 . The method according to  claim 42 , wherein doping the dielectric layer comprises doping with an ion beam,  
   
   
       44 . The method according to  claim 42 , wherein doping the dielectric layer comprises: 
 providing a mask layer over the conductive material of the first region;    doping the device with Al ions; and    removing the mask layer.    
   
   
       45 . The method according to  claim 42 , wherein subjecting the device to a thermal treatment forms an Al 2 O 3  layer.  
   
   
       46 . The method according to  claim 42 , wherein the conductive material comprises N+ doped polysilicon.  
   
   
       47 . The method of  claim 1 , wherein the polysilicon gate comprises an n-doped polysilicon gate.