Thin film transistor substrate and method for forming metal wire thereof

Abstract

The present invention relates to a thin film transistor substrate and a metal wiring method thereof, more particularly to a thin film transistor substrate comprising self-assembled monolayers between the substrate and the metal wiring, and a metal wiring thereof. Since a thin film transistor substrate of the present invention comprises three-dimensionally cross-linked self-assembled monolayers between the Si surface and the metal wiring, it has good adhesion ability and anti-diffusion ability.

1 - 13 . (canceled)  
   
   
       14 . A method for forming self-assembled monolayers (SAMs) of a thin film transistor substrate, comprising steps of: 
 coating self-assembled monolayer forming material dissolved in a solvent on a substrate and heat-treating; and    depositing a Cu layer as a metal wiring material on the heat-treated substrate to form self-assembled monolayers having a three-dimensionally cross-linked structure between the substrate and the metal wiring.    
   
   
       15 . The method of  claim 14 , wherein the self-assembled monolayers are formed by a compound selected from the group consisting of 3-aminopropyltrimethoxysilane, 3-aminopropyltriethoxysilane, 2-aminoundecyltrimethoxysilane, aminophenyltrimethoxysilane, N-(2-aminoethylaminopropyl)trimethoxysilane, methyltrimethoxysilane, propyltriacetoxysilane, (3-mercaptopropyl)trimethoxysilane, and (3-mercaptopropyl)trimethoxysilane.  
   
   
       16 . The method of  claim 14 , wherein the mixing ratio of the self-assembled monolayer forming material and the solvent is 1:20 to 1:30 by weight.  
   
   
       17 . The method of  claim 14 , wherein the heat treatment is performed at a temperature of 100 to 300° C.  
   
   
       18 . The method of  claim 14 , wherein the solvent is selected from the group consisting of methanol, ethanol, propanol, butanol, cellusolv, dimethylformamide, and water.  
   
   
       19 . A method for forming self-assembled monolayers (SAMs) of a thin film transistor substrate, comprising steps of: 
 coating self-assembled monolayer forming material dissolved in a solvent on a substrate and heat-treating; and    depositing a copper alloy layer as a metal wiring material on the heat-treated substrate to form self-assembled monolayers having a three-dimensionally cross-linked structure between the substrate and the metal wiring, wherein the copper alloy comprises copper and a metal that has superior anti-diffusion ability and is not significantly soluble to the substrate, and has a lower surface energy than copper.    
   
   
       20 . The method of  claim 19 , wherein the metal is Ag, Mg, B, Ca, Al, Li, Np, Pu, Ce, Eu, Pr, La, Nd, Sm, Zn, or any mixture thereof.  
   
   
       21 . A thin film transistor substrate comprising: 
 an insulation substrate;    a first signal line formed on the insulation substrate;    a first insulation film formed on the first signal line;    a second signal line formed on the first insulation film and crossing the first signal line;    a thin film transistor electrically connected with the first signal line and the second signal line;    a second insulation film formed on the thin film transistor and having a first contact opening that exposes an electrode of the thin film transistor; and    a pixel electrode formed on the second insulation film and connected to the electrode of the thin film transistor through the first contact opening, wherein at least one of the first signal line and the second signal line has a copper alloy wiring structure consisting of a triple-layer of self-assembled monolayers, a metal layer that has superior anti-diffusion ability, is not significantly soluble to the substrate, and has a lower surface energy than copper, and a Cu layer.    
   
   
       22 . The method of  claim 21 , wherein the metal layer comprises Ag, Mg, B, Ca, Al, Li, Np, Pu, Ce, Eu, Pr, La, Nd, Sm, Zn, or any mixture thereof.  
   
   
       23 . A thin film transistor substrate comprising: 
 a gate wiring formed on an insulation substrate and comprising a gate line and a gate electrode connected to the gate line;    a gate insulation film covering the gate wiring;    a semiconductor pattern formed on the gate insulation film;    a data wiring comprising a source electrode and a drain electrode formed in the same layer on the gate insulation film or on the semiconductor pattern and that are separated from each other, and a data line connected to the source electrode and crossing the gate line to define a pixel area;    a protection film having a first contact opening that exposes the drain electrode; and    a pixel electrode formed on the protection film and connected with the drain electrode through the first contact opening,    wherein at least one of the gate wiring and the data wiring has a copper alloy wiring structure consisting of a triple-layer of self-assembled monolayers, a metal layer that has superior anti-diffusion ability, is not significantly soluble to the substrate, and has a lower surface energy than copper, and a Cu layer.    
   
   
       24 . The method of  claim 23 , wherein the metal layer comprises Ag, Mg, B, Ca, Al, Li, Np, Pu, Ce, Eu, Pr, La, Nd, Sm, Zn, or any mixture thereof.  
   
   
       25 . A thin film transistor substrate comprising: 
 an insulation substrate;    a gate wiring formed on the substrate and comprising a gate line, a gate electrode, and an end part of the gate line;    a gate insulation film formed on the gate wiring and having a contact opening that exposes the end part of the gate line;    a semiconductor pattern formed on the gate insulation film;    a data wiring comprising a source electrode, a drain electrode, a data line, and an end part of the data line that has a contact layer pattern on the gate insulation film or on the semiconductor pattern;    a protection film formed on the data wiring and having contact openings that expose the end part of the gate line, the end part of the data line, and the drain electrode; and    a transparent electrode layer pattern electrically connected with the exposed end part of the gate line, end part of the data line, and drain electrode, wherein at least one of the gate wiring and the data wiring has a copper alloy wiring structure consisting of a triple-layer of self-assembled monolayers, a metal layer that has superior anti-diffusion ability, is not significantly soluble to the substrate, and has a lower surface energy than copper, and a Cu layer.    
   
   
       26 . The method of  claim 25 , wherein the metal layer comprises Ag, Mg, B, Ca, Al, Li, Np, Pu, Ce, Eu, Pr, La, Nd, Sm, Zn, or any mixture thereof.