Methods and apparatus for reducing command processing latency while maintaining coherence

Abstract

In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.

1 .- 22 . (canceled)  
   
   
       23 . A method of processing commands, comprising: 
 providing a system comprising a plurality of chips;    providing a memory map including memory addresses available to the system; and    arranging the memory addresses into a plurality of groups so that: 
 a first of the plurality of groups corresponds to a subset of memory addresses associated with a first chip in the system; and  
 if a coherent command from a bus unit in the first chip requires access to a memory address in the first group, the coherent command is treated as non-coherent.  
   
   
   
       24 . The method of  claim 23  wherein, if the coherent command is treated as non-coherent, the system is not required to obtain permission from all remaining bus units included in the system to access the memory address.  
   
   
       25 . The method of  claim 23  further comprising: 
 receiving a coherent command from the bus unit in the first chip that requires access to a memory address in the first group; and    employing the memory map to treat the command as non-coherent.    
   
   
       26 . The method of  claim 25  further comprising reducing latency while processing the command.  
   
   
       27 . The method of  claim 23  further comprising: 
 receiving a coherent command from the bus unit in the first chip that requires access to a memory address which is not in the first group; and    employing the memory map to treat the command as coherent.    
   
   
       28 . The method of  claim 27  wherein treating the command as coherent includes requiring the system to obtain permission from all remaining bus units included in the system to access the memory address.  
   
   
       29 . An apparatus for processing commands, comprising: 
 logic adapted to store a memory map including memory addresses available to a system comprising a plurality of chips;    wherein the memory addresses are arranged into a plurality of groups so that: 
 a first of the plurality of groups corresponds to a subset of memory addresses associated with a first chip in the system; and  
 if a coherent command from a bus unit in the chip requires access to a memory address in the first group, the coherent command is treated as non-coherent.  
   
   
   
       30 . The apparatus of  claim 29  wherein the memory addresses in the memory map are arranged into a first group which corresponds to a subset of memory addresses associated with the first chip in the system and a second group which corresponds to remaining addresses available to the system.  
   
   
       31 . The apparatus of  claim 29  wherein, if the coherent command is treated as non-coherent, the system is not required to obtain permission from all remaining bus units included in the system to access the memory address.  
   
   
       32 . The apparatus of  claim 29  wherein the logic is further adapted to: 
 receive a coherent command from the bus unit in the first chip that requires access to a memory address in the first group; and    employ the memory map to treat the command as non-coherent.    
   
   
       33 . The apparatus of  claim 32  wherein the memory map is adapted to reduce latency while processing the command.  
   
   
       34 . The apparatus of  claim 29  wherein the logic is further adapted to: 
 receive a coherent command from the bus unit in the first chip that requires access to a memory address which is not in the first group; and    employ the memory map to treat the command as coherent.    
   
   
       35 . The apparatus of  claim 34  wherein the memory map is adapted to require the system to obtain permission from all remaining bus units included in the system to access the memory address.  
   
   
       36 . A computer program product, comprising: 
 a medium readable by a computer, the computer readable medium having computer program code adapted to: 
 provide a memory map including memory addresses available to a system comprising a plurality of chips; and  
 arrange the memory addresses into a plurality of groups so that: 
 a first of the plurality of groups corresponds to a subset of memory addresses associated with a first chip in the system; and  
 if a coherent command from a bus unit in the first chip requires access to a memory address in the first group, the coherent command is treated as non-coherent.  
 
   
   
   
       37 . The computer program product of  claim 36  wherein the memory map is adapted to: 
 be employed to process the coherent command from the bus unit in the first chip that requires access to a memory address in the first group; and    reduce latency while processing the coherent command by treating the command as non-coherent.    
   
   
       38 . A system for processing commands, comprising: 
 a plurality of chips;    a plurality of bus units, wherein two or more of the bus units may be on different chips, cards or computers of the system;    a plurality of buses coupling the bus units;    a plurality of memories, each of which corresponds to one or more of the bus units; and    logic adapted to store a memory map including memory addresses available to the system;    wherein the memory addresses are arranged into a plurality of groups so that: 
 a first group of the plurality of groups corresponds to a subset of memory addresses associated with a first chip in the system; and  
 if a coherent command from a bus unit in the first chip requires access to a memory address in the first group, the coherent command is treated as non-coherent.  
   
   
   
       39 . The system of  claim 38  wherein the memory addresses are arranged into a first group which corresponds to a subset of memory addresses associated with the first chip in the system and a second group which corresponds to remaining addresses available to the system.  
   
   
       40 . The system of  claim 38  wherein, if the coherent command is treated as non-coherent, the system is not required to obtain permission from all remaining bus units included in the system to access the memory address.  
   
   
       41 . The system of  claim 38  wherein the logic is further adapted to: 
 receive the coherent command from the bus unit in the first chip that requires access to a memory address in the first group; and    employ the memory map to treat the coherent command as non-coherent.    
   
   
       42 . The system of  claim 41  wherein the memory map is adapted to reduce latency while processing the command.  
   
   
       43 . The system of  claim 38  wherein the logic is further adapted to: 
 receive the coherent command from the bus unit in the first chip that requires access to a memory address which is not in the first group; and    employ the memory map to treat the command as coherent.    
   
   
       44 . The system of  claim 43  wherein the memory map is adapted to require the system to obtain permission from all remaining bus units included in the system to access the memory address to process the command.