Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes

Abstract

A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, depositing a conventional dielectric on the surface surrounding the carbon nanotubes, and then removing the carbon nanotubes to produce the voids. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. Recesses formed in the dielectric for conductors are lined with a non-conformal dielectric film to seal the voids. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

1 . An integrated circuit chip having a plurality of substantially planar parallel layers deposited over a substrate, including: 
 a first plurality of substantially planar parallel conductor layers, each conductor layer comprising a plurality of discrete conductors separated by a dielectric;    a second plurality of substantially planar parallel insulative layers, each insulative layer comprising a dielectric penetrated by a plurality of conductive vias;    wherein at least one layer comprises a dielectric structure containing: (a) a plurality of cylindrical voids formed therein, said cylindrical voids being oriented perpendicular to said at least one layer, and (b) a plurality of conductors formed of a conductive material in recesses of said dielectric structure, said recesses having vertical walls lined with a conformal film dielectric to seal said cylindrical voids from said conductive material.    
     
     
         2 . The integrated circuit chip of  claim 1 , wherein said cylindrical voids are substantially smaller than said conductive vias.  
     
     
         3 . The integrated circuit chip of  claim 2 , wherein said cylindrical voids have a diameter of less than 50 nm.  
     
     
         4 . The integrated circuit chip of  claim 3 , wherein said cylindrical voids have a diameter of less than 30 nm.  
     
     
         5 . The integrated circuit chip of  claim 1 , wherein said at least one layer comprising a dielectric structure is at least one layer of said first plurality of layers.  
     
     
         6 . The integrated circuit chip of  claim 1 , wherein said at least one layer comprising a dielectric structure is at least one layer of said second plurality of layers.  
     
     
         7 . The integrated circuit chip of  claim 1 , wherein said chip comprises a plurality of said layers comprising a dielectric structure, each said layer containing a respective plurality of said cylindrical voids and a respective plurality of said conductors formed of a conductive material in recesses of said dielectric structure, said recesses having vertical walls lined with a conformal film dielectric to seal said cylindrical voids from said conductive material.  
     
     
         8 . The integrated circuit chip of  claim 1 , wherein said cylindrical voids are formed by a process of forming a plurality of carbon nanotube form structures, depositing a dielectric material surrounding said carbon nanotube form structures, and removing said carbon nanotube form structures to form said cylindrical voids in said dielectric material.  
     
     
         9 . A computer system having a plurality of functional units, at least one of said functional units embodied in an integrated circuit chip having a plurality of substantially planar parallel layers deposited over a substrate, said integrated circuit chip including: 
 a first plurality of substantially planar parallel conductor layers, each conductor layer comprising a plurality of discrete conductors separated by a dielectric;    a second plurality of substantially planar parallel insulative layers, each insulative layer comprising a dielectric penetrated by a plurality of conductive vias;    wherein at least one layer comprises a dielectric structure containing: (a) a plurality of cylindrical voids formed therein, said cylindrical voids being oriented perpendicular to said at least one layer, and (b) a plurality of conductors formed of a conductive material in recesses of said dielectric structure, said recesses having vertical walls lined with a conformal film dielectric to seal said cylindrical voids from said conductive material.    
     
     
         10 . The computer system of  claim 9 , wherein said integrated circuit chip embodies at least one processor of said computer system.  
     
     
         11 . The computer system of  claim 9 , wherein said integrated circuit chip embodies at least a portion of memory of said computer system.  
     
     
         12 . The computer system of  claim 9 , wherein said cylindrical voids are substantially smaller than said conductive vias.  
     
     
         13 . The computer system of  claim 9 , wherein said at least one layer comprising a dielectric structure is at least one layer of said first plurality of layers.  
     
     
         14 . The computer system of  claim 9 , wherein said at least one layer comprising a dielectric structure is at least one layer of said second plurality of layers.  
     
     
         15 . The computer system of  claim 9 , wherein said cylindrical voids are formed by a process of forming a plurality of carbon nanotube form structures, depositing a dielectric material surrounding said carbon nanotube form structures, and removing said carbon nanotube form structures to form said cylindrical voids in said dielectric material.