Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same

Abstract

According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.

1 . A method for fabricating a semiconductor device comprising: 
 sequentially stacking a buried insulating layer and an upper silicon pattern on an active area of a lower semiconductor substrate;    electrically connecting the upper silicon pattern to the lower semiconductor substrate with a through plug that penetrates the buried insulating layer; and    forming a MOS transistor that includes source/drain regions separated by a body region, one of the source/drain regions positioned closer to the through plug than another one of the source/drain regions, an upper surface of the through plug structured to be outside a depletion layer when a source voltage is applied to the one of the source/drain regions, the upper surface of the through plug structured to be inside the depletion layer when a drain voltage is applied to the one region.    
   
   
       2 . The method of  claim 1 , wherein forming the MOS transistor comprises: 
 forming a gate electrode on the upper silicon pattern that is insulated from the upper silicon pattern; and    implanting impurity ions using the gate electrode as an ion implanting mask to form the source/drain regions.    
   
   
       3 . The method of  claim 2 , wherein sequentially stacking the buried insulating layer and the upper silicon pattern comprises: 
 forming a sacrificial layer on the lower semiconductor substrate;    patterning the sacrificial layer to form an opening that exposes the lower semiconductor substrate;    filling the opening and covering the sacrificial layer with an upper silicon epitaxial layer;    patterning the upper silicon epitaxial layer, the sacrificial layer, and the lower semiconductor substrate to form a trench that defines the active area within the lower semiconductor substrate, the active area including some portion of the lower semiconductor substrate exposed by the opening, the patterned sacrificial layer being exposed by side walls of the trench;    selectively removing the exposed patterned sacrificial layer to form an empty space;    depositing the buried insulating layer within the empty space; and    depositing a device isolation layer within the trench.    
   
   
       4 . The method of  claim 3 , wherein forming the sacrificial layer comprises forming a SiGe epitaxial layer.  
   
   
       5 . The method of  claim 3 , further comprising: 
 forming a lower silicon epitaxial layer on the sacrificial layer.    
   
   
       6 . The method of  claim 1 , wherein the source/drain regions are separated from the buried insulating layer by the body region.  
   
   
       7 . The method of  claim 1 , wherein the one of the source/drain regions is positioned above the through plug.  
   
   
       8 . The method of  claim 1 , wherein the source/drain regions are in contact with the buried insulating layer.  
   
   
       9 . The method of  claim 2 , further comprising: 
 before forming the gate electrode, implanting channel ions on the upper silicon pattern; and    performing thermal treatment on the upper silicon pattern to diffuse the channel ions,    wherein the channel ions are diffused via the through plug, and a concentration of channel ions within the body region above the through plug is less than a concentration of channel ions within the body region above the buried insulating layer.    
   
   
       10 . The method of  claim 2 , wherein sequentially stacking the buried insulating layer and the upper silicon pattern comprises: 
 sequentially stacking the lower semiconductor substrate, the buried insulating layer, and a lower silicon layer to prepare an SOI substrate;    sequentially patterning the lower silicon layer and the buried insulating layer to form an opening that exposes the lower semiconductor substrate;    filling the opening and covering the lower silicon layer with an upper silicon epitaxial layer;    sequentially patterning the upper silicon epitaxial layer, the lower silicon layer, the buried insulating layer, and the lower semiconductor substrate to form a trench that defines the active area within the lower semiconductor substrate, the active area including at least some portion of the lower semiconductor substrate exposed by the opening; and    filling the trench with a device isolation layer.    
   
   
       11 . The method of  claim 10 , wherein the source/drain regions are separated from the buried insulating layer by the body region.  
   
   
       12 . The method of  claim 11 , wherein the one of the source/drain regions is positioned above the through plug.