US2007184595A1PendingUtilityA1
Semiconductor device and manufacturing method thereof
Est. expiryOct 7, 2023(expired)· nominal 20-yr term from priority
H10P 50/283H10W 20/0698H10W 20/081H10D 1/68H10B 53/30H10B 53/00
50
PatentIndex Score
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Claims
Abstract
An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.
Claims
exact text as granted — not AI-modified1 - 6 . (canceled)
7 . A manufacturing method of a semiconductor device, comprising the steps of:
forming a ferroelectric capacitor above a substrate; forming an interlayer insulating film which covers said ferroelectric capacitor; forming a hole reaching an electrode of said ferroelectric capacitor through said interlayer insulating film; and forming a wiring which is connected to said electrode through said hole above said interlayer insulating film, in the step of forming said hole, a planar shape of said hole being any one type selected from a group consisting of: (1) a polygon with an interior angle of each angle thereof being obtuse; (2) a closed curve with a bending direction thereof being constantly inward with respect to said hole; and (3) a shape which consists of a line segment and a curve with a bending direction thereof being constantly inward with respect to said hole, an angle between a tangent of said curve and said line segment at an intersection of said line segment and said curve being obtuse, and an interior angle of an intersection of two of said line segments being obtuse.
8 . The manufacturing method of a semiconductor device according to claim 7 , wherein a shortest diameter of said hole is 1.0 μm or more.
9 . The manufacturing method according to claim 7 , wherein said wiring is an aluminum wiring, and a barrier metal film is formed between said wiring and said electrode before forming such a wiring.
10 . The manufacturing method according to claim 8 , wherein said wiring is an aluminum wiring, and a barrier metal film is formed between said wiring and said electrode before forming such a wiring.
11 . The manufacturing method according to claim 9 , wherein said barrier metal film is a titanium nitride film.
12 . The manufacturing method according to claim 10 , wherein said barrier metal film is a titanium nitride film.
13 . The manufacturing method according to claim 7 , wherein said electrode contains a metal of a platinum family or an oxide thereof.
14 . The manufacturing method according to claim 8 , wherein said electrode contains a metal of a platinum family or an oxide thereof.
15 . The manufacturing method according to claim 9 , wherein said electrode contains a metal of a platinum family or an oxide thereof.
16 . The manufacturing method according to claim 10 , wherein said electrode contains a metal of a platinum family or an oxide thereof.
17 . The manufacturing method according to claim 11 , wherein said electrode contains a metal of a platinum family or an oxide thereof.
18 . The manufacturing method according to claim 12 , wherein said electrode contains a metal of a platinum family or an oxide thereof.
19 . The manufacturing method according to claim 7 , wherein a planar shape of said hole is a circle, or a regular polygon whose number of angles is identical to or more than five.
20 . The manufacturing method according to claim 7 , wherein the step of forming said hole comprises the steps of:
forming a mask having an opening portion, a planar shape of which being identical to that of said hole to be formed; performing etching of said interlayer insulating film by using said mask; and removing said mask.Join the waitlist — get patent alerts
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