NAND-type nonvolatile memory devices having common bit lines and methods of operating the same

Abstract

A NAND-type nonvolatile memory device includes a first string and a second string. The ends of each of the first and second strings are connected to a common bit line and a common source line, respectively. Each of the first string and the second string have a string selection transistors, a plurality of unit devices and a source selection transistor. Word lines are respectively connected to control gates of the unit devices in the same rows. A first string selection line and a second string selection line are respectively connected to the gates of the string selection transistors of the first string and the second string. A first source selection line and a second source selection line are respectively connected to the gates of the first string and the second string.

1 . A nonvolatile memory device comprising:
 a first pair of strings including,
 a first string having a first string selection transistor, a plurality of first unit devices and a first source selection transistor connected in series; 
 a second string having a second string selection transistor, a plurality of second unit devices, and a second source selection transistors connected in series; 
   a plurality of word lines, each word line being connected to a control gate of a first unit device and a control gate of a corresponding second unit, the first and corresponding second unit device being located in a same row of the first string and the second string;   a first common bit line connecting one end of each of the first string and the second string; and   a first common source line connecting another end of the first string and the second string.   
   
   
       2 . The nonvolatile memory device of  claim 1 , the device further including,
 a first string selection line connected to a gate of the first string selection transistor, and   a second string selection line connected to a gate of the second string selection transistor.   
   
   
       3 . The nonvolatile memory device of  claim 2 , wherein the first string selection line and the second string selection line traverse the first and second strings in different rows. 
   
   
       4 . The nonvolatile memory device of  claim 1 , the device further including,
 a first source selection line connected to a gate of the first source selection transistor, and   a second source selection line connected to a gate of the second source selection transistor.   
   
   
       5 . The nonvolatile memory device of  claim 4 , wherein the first source selection line and the second source selection line traverse the first and second strings in different rows. 
   
   
       6 . The nonvolatile memory device of  claim 1 , wherein at least one of the plurality of first unit devices and the plurality of second unit devices have a unit cell structure of a flash memory device or a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory device. 
   
   
       7 . The nonvolatile memory device of  claim 1 , further including,
 at least one second pair of strings, the second pair of strings including,
 a third string including a third string selection transistor, a plurality of third unit devices and a third source selection transistor connected in series, and 
 a fourth string including a fourth string selection transistor, a plurality of fourth unit devices, and a fourth source selection transistors connected in series; 
   at least one second common bit line connecting one end of each of the third string and the fourth string; and   at least one second common source line connecting another end of the third string and the fourth string, wherein
 each of the plurality of word lines are connected to a control gate of the first unit device, a control gate of a corresponding second unit device, a control gate of the corresponding third unit device and a control gate of a corresponding fourth unit device, the corresponding first, second, third and fourth unit devices being located on the same row of the first, second, third and fourth string, respectively. 
   
   
   
       8 . The nonvolatile memory device of  claim 7 , wherein the first string selection line is connected to a gate of the third string selection transistor, and the second string selection line is further connected to a gate of the fourth string selection transistor. 
   
   
       9 . The nonvolatile memory device of  claim 8 , wherein the first string selection line and the second string selection line traverse the first and second strings in different rows, and the third string selection line and the fourth string selection line traverse the third and fourth strings in different rows. 
   
   
       10 . The nonvolatile memory device of  claim 7 , wherein the first source selection line is further connected to a gate of the third source selection transistor and the second source selection line is further connected to a gate of the fourth source selection transistor. 
   
   
       11 . The nonvolatile memory device of  claim 7 , wherein the first string selection line and the second string selection line are arranged in different rows. 
   
   
       12 . The nonvolatile memory device of  claim 7 , wherein the plurality of unit devices have a unit cell structure of a flash memory device or a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory device. 
   
   
       13 . The nonvolatile memory device of  claim 7 , wherein the plurality of common source lines are electrically connected to one another. 
   
   
       14 . A method of operating a nonvolatile memory device, the method comprising:
 selectively storing data in one of a plurality of unit devices of a first pair of strings by supplying a first voltage to a channel of a plurality of unit devices of a first string, supplying a second voltage to a channel of a plurality of unit devices of a second string, supplying a third voltage to a word line connected to a gate of the one of the plurality of unit devices in which data is to be stored, and supplying a fourth voltage to word lines connected to gates of the other of the plurality of unit devices; and   reading data stored in the one of the plurality of unit devices; wherein
 the first and the second voltage are different. 
   
   
   
       15 . The method of  claim 14 , wherein the first voltage enables selective storing of data in the one of the plurality of unit devices, and the second voltage prevents selective storing of data in the other of the plurality of unit devices. 
   
   
       16 . The method of  claim 14 , wherein the selectively storing further includes,
 supplying the second voltage to one of a common bit line connecting one end of each of the first string and the second string a common source line connecting another end of the first string and the second string, and supplying the first voltage the other of the common source line and the common bitline,   supplying a turn-off voltage to a string selection line connected to a gate of the string selection transistor of the first string, and supplying a turn-on voltage to a string selection line connected to the string selection transistor of the second string, and   supplying the turn-on voltage to a source selection line connected to a gate of the source selection transistor of the first string, and supplying a turn-off voltage to a source selection line connected to the string selection transistor of the second string.   
   
   
       17 . The method of  claim 14 , wherein the reading includes,
 supplying the second voltage to one of a common bit line connecting one end of each of the first string and the second string a common source line connecting another end of the first string and the second string, and supplying the first voltage the other of the common source line and the common bitline,   supplying the turn-on voltage a string selection line connected to a gate of the string selection transistor of the first string, and supplying a turn-on voltage to a string selection line connected to the string selection transistor of the second string;   supplying the turn-on voltage to the source selection line connected to a gate of the source selection transistor of the first string, and supplying a turn-off voltage to a source selection line connected to the string selection transistor of the second string;   supplying the turn-off voltage to the string selection line connected to the gate of the string selection transistor of the second string and to the source selection line connected to the gate of the source selection transistor of the second string; and   supplying a read voltage to the word line connected to a gate of one of the plurality of unit devices of the first string, and supplying a pass voltage to the word lines connected to gates of the other of the plurality of unit devices.   
   
   
       18 . The method of  claim 14 , further including,
 block erasing data of the plurality of unit devices of the first string and the second string.   
   
   
       19 . The method of  claim 18 , wherein the block erasing is performed simultaneously. 
   
   
       20 . The method of  claim 14 , wherein the first voltage is lower than the second voltage.