Metal capacitor including lower metal electrode having hemispherical metal grains

Abstract

Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains containing Pd and formed on the lower metal electrode containing Ti, a dielectric layer formed on the lower metal electrode containing Ti and the hemispherical metal grains containing Pd, and an upper metal electrode formed on the dielectric layer.

1 . A metal capacitor comprising:
 a lower metal electrode containing titanium;   hemispherical metal grains containing palladium disposed on an upper surface of the lower metal electrode;   a dielectric layer formed on the lower metal electrode and the hemispherical metal grains; and   an upper metal electrode formed on the dielectric layer.   
   
   
       2 . The metal capacitor of  claim 1 , wherein the lower metal electrode is a TiN electrode. 
   
   
       3 . The metal capacitor of  claim 1 , further comprising an insulating layer formed beneath the lower metal electrode and a titanium layer interposed between the lower metal electrode and the insulating layer. 
   
   
       4 . The metal capacitor of  claim 1 , further comprising hemispherical metal grains formed on a side surface of the lower metal electrode. 
   
   
       5 . The metal capacitor of  claim 1 , wherein the dielectric layer is formed on the upper surface and side surface of the lower metal electrode, and the upper metal electrode is disposed to cover the substantially entire dielectric layer. 
   
   
       6 . The metal capacitor of  claim 1 , further comprising:
 an upper insulating layer disposed on the upper metal electrode;   a first via plug in the upper insulating layer contacting the lower metal electrode;   a second via plug in the upper insulating layer contacting the upper metal electrode; and   a plurality of wiring lines disposed on the upper insulating layer and contacting the first and second via plugs.   
   
   
       7 . The metal capacitor of  claim 1 , wherein the dielectric layer comprises one of hafnium oxide, aluminum oxide, and silicon oxide. 
   
   
       8 . A metal capacitor comprising:
 a plurality of transistors formed on a substrate;   a first insulating layer disposed on the plurality of transistors;   a via plug formed through the first insulating layer to be electrically connected to the substrate;   a second insulating layer disposed on the first insulating layer and having a hole exposing an upper surface of the via plug;   a lower metal electrode containing titanium, which is disposed to contact the exposed upper surface of the via plug and a side wall of the hole, the lower metal electrode having an inner wall and an outer wall;   hemispherical metal grains containing palladium and formed on the lower metal electrode;   a dielectric layer formed on the lower metal electrode and the hemispherical metal grains; and   an upper metal electrode formed on the dielectric layer.   
   
   
       9 . The metal capacitor of  claim 8 , wherein the lower metal electrode is formed of TiN, and further comprising a titanium layer interposed between the lower metal electrode and the hole. 
   
   
       10 . The metal capacitor of  claim 8 , wherein the width of the hole is larger than the upper surface of the via plug. 
   
   
       11 . The metal capacitor of  claim 8 , wherein the hemispherical metal grains are disposed on the inner wall, the outer wall and the upper surface of the metal electrode. 
   
   
       12 . A method of fabricating a metal capacitor, the method comprising:
 forming a lower metal electrode containing titanium;   dipping the lower metal electrode into an electrolyte solution containing palladium, thereby forming hemispherical metal grains containing palladium on the lower metal electrode;   forming a dielectric layer on the lower metal electrode; and   forming an upper metal electrode on the dielectric layer.   
   
   
       13 . The method of  claim 12 , wherein the lower metal electrode is formed of TiN. 
   
   
       14 . The method of  claim 12 , further comprising forming an insulating layer beneath the lower metal electrode, and forming a titanium layer between the lower metal electrode and the insulating layer. 
   
   
       15 . The method of  claim 12 , wherein the electrolyte solution is an acidic electrolyte solution comprising palladium chloride (PdCl 2 ), hydrofluoric acid, hydrochloric acid, a reducing agent, and a complexing agent. 
   
   
       16 . The method of  claim 15 , wherein the reducing agent is glacial acetic acid, and the complexing agent is ethylene-diamine-tetra-acetic acid. 
   
   
       17 . The method of  claim 15 , wherein the electrolyte solution comprises about 0.001 to 0.1 wt % of palladium chloride (PdCl 2 ), about 0.01 to 1 wt % of 40 to 60% diluted hydrofluoric acid, about 0.047 to 4.7 wt % of 30 to 50% diluted hydrochloric acid, about 0.2 to 23 wt % of the reducing agent, and about 0.002 to 0.25 wt % of the complexing agent. 
   
   
       18 . A method of fabricating a metal capacitor, the method comprising:
 forming a plurality of transistors on a substrate;   forming a first insulating layer on the plurality of transistors;   forming a conductive via plug through the first insulating layer to contact the substrate;   forming a second insulating layer on the first insulating layer and the via plug;   forming a third insulating layer on the second insulating layer;   forming a hole through the second insulating layer and the third insulating layer thereby exposing the via plug;   forming a lower metal electrode containing titanium within the hole;   dipping the lower metal electrode into an electrolyte solution containing palladium, thereby forming hemispherical metal grains containing palladium on the lower metal electrode;   forming a dielectric layer on the lower metal electrode; and   forming an upper metal electrode on the dielectric layer.   
   
   
       19 . The method of  claim 18 , wherein the first insulating layer and the third insulating layer are formed of silicon oxide, and the second insulating layer is formed of silicon nitride. 
   
   
       20 . The method of  claim 18 , further comprising forming a titanium layer between the lower metal electrode and the hole, wherein the lower metal electrode is formed of TiN. 
   
   
       21 . The method of  claim 18 , wherein the electrolyte solution is an acidic electrolyte solution comprising palladium chloride (PdCl 2 ), hydrofluoric acid, hydrochloric acid, a reducing agent, and a complexing agent. 
   
   
       22 . The method of  claim 21 , wherein the reducing agent is glacial acetic acid, and the complexing agent is ethylene-diamine-tetra-acetic acid. 
   
   
       23 . The method of  claim 22 , wherein the electrolyte solution comprises about 0.001 to 0.1 wt % of palladium chloride (PdCl 2 ), about 0.01 to 1 wt % of 40 to 60% diluted hydrofluoric acid, about 0.047 to 4.7 wt % of 30 to 50% diluted hydrochloric acid, about 0.2 to 23 wt % of the reducing agent, and about 0.002 to 0.25 wt % of the complexing agent. 
   
   
       24 . The method of  claim 18 , wherein dipping the lower metal electrode into the electrolyte solution is conducted using the electrolyte solution at about 50 to 90° C. for about 1 to 5 min. 
   
   
       25 . The method of  claim 24 , wherein the electrolyte solution comprises palladium chloride, the complexing agent, hydrofluoric acid, hydrochloric acid, and the reducing agent at weight ratios of about (0.05 to 5):(0.125 to 12.5):(0.5 to 50):(2.5 to 250):(12.5 to 1250).