Data-dependent jitter pre-emphasis for high-speed serial link transmitters

Abstract

In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.

1 . An apparatus for providing data dependent jitter in data transmission, said apparatus comprising: 
 an input arrangement for accepting data input;    an arrangement for detecting and decoding transitions in the data input;    said arrangement for detecting and decoding being adapted to ascertain data transition history in the data input; and    an arrangement for applying at least one delay to at least a portion of the data input, based on the ascertained data transition history.    
   
   
       2 . The apparatus according to  claim 1 , wherein the input data comprises a serial data stream.  
   
   
       3 . The apparatus according to  claim 2 , wherein said input arrangement comprises a plurality of single data bit delay elements for successively delaying the serial data stream of the input data.  
   
   
       4 . The apparatus according to  claim 3 , wherein said detecting and decoding arrangement comprises a plurality of XOR gates for comparing portions of the serial data stream at different sampling positions among said plurality of single data bit delay elements.  
   
   
       5 . The apparatus according to  claim 2 , wherein said arrangement for applying at least one delay is adapted to add or subtract a pre-distortion delay to the serial data stream of the input data.  
   
   
       6 . The apparatus according to  claim 1 , wherein the data input comprises a plurality of parallel partial-rate data streams.  
   
   
       7 . The apparatus according to  claim 6 , wherein said input arrangement comprises a plurality of receiving elements for aligning the partial-rate data streams to a local clock.  
   
   
       8 . The apparatus according to  claim 6 , wherein: 
 said detecting and decoding arrangement is adapted to influence the partial-rate data streams to determine a data sequence to be subsequently transmitted in an output serial data stream; and    said detecting and decoding arrangement is adapted to generate a code informing an amount of pre-phase distortion to be applied to the input data.    
   
   
       9 . The apparatus according to  claim 6 , wherein said arrangement for applying at least one delay is adapted to pre-distort the phase of a clock used in transitioning the partial-rate data streams into an output serial data stream.  
   
   
       10 . The apparatus according to  claim 6 , wherein the data input comprises a plurality of parallel quarter-rate data streams.  
   
   
       11 . A method of providing data dependent jitter in data transmission, said method comprising the steps of: 
 accepting data input;    detecting and decoding transitions in the data input;    said step of detecting and decoding comprising ascertaining data transition history in the data input; and    applying at least one delay to at least a portion of the data input, based on the ascertained data transition history.    
   
   
       12 . The method according to  claim 11 , wherein the data input comprises a serial data stream.  
   
   
       13 . The method according to  claim 12 , wherein said accepting step comprises accepting a plurality of single data bit delay elements for successively delaying the serial data stream of the input data.  
   
   
       14 . The method according to  claim 13 , wherein said detecting and decoding step comprises comparing portions of the serial data stream at different sampling positions among the plurality of single data bit delay elements.  
   
   
       15 . The method according to  claim 12 , wherein said step of applying at least one delay comprises adding or subtracting a pre-distortion delay to the serial data stream of the input data.  
   
   
       16 . The method according to  claim 11 , wherein the data input comprises a plurality of parallel partial-rate data streams.  
   
   
       17 . The method according to  claim 16 , wherein said input step comprises aligning the partial-rate data streams to a local clock.  
   
   
       18 . The method according to  claim 16 , wherein: 
 said detecting and decoding step comprises influencing the partial-rate data streams to determine a data sequence to be subsequently transmitted in an output serial data stream; and    said detecting and decoding step comprises generating a code informing an amount of pre-phase distortion to be applied to the input data.    
   
   
       19 . The method according to  claim 16 , wherein said step of applying at least one delay comprises pre-distorting the phase of a clock used in transitioning the partial-rate data streams into an output serial data stream.  
   
   
       20 . The method according to  claim 16 , wherein the data input comprises a plurality of parallel quarter-rate data streams.