Semiconductor storage device and method of fabricating the same

Abstract

A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3 a , 3 b, a second gate wiring element 3 c, 3 d, a first connector 5 a, 5 b, and a second connector 5 c, 5 d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

1 . A semiconductor storage device comprising: 
 a memory cell array comprising memory cells each having first and second driver transistors, first and second load transistors, and first and second access transistors, the memory cells being two-dimensionally arranged on a semiconductor substrate;    a plurality of word lines connected to the memory cells and arranged in parallel to each other along a first direction;    a plurality of bit lines connected to the memory cells, the bit lines being arranged in parallel to each other along a second direction perpendicular to the first direction;    a first gate wiring element composing a gate electrode of the first driver transistor and the first load transistor, and having a rectangular shape having straight line on opposite sides;    a second gate wiring element composing a gate electrode of the access transistor, and having a rectangular shape having straight line on opposite sides;    a first connector connecting the first gate wiring element, an active region of the second driver transistor, and an active region of the second load transistor to each other; and    a second connector connecting the second gate wiring element to the word lines to each other.    
   
   
       2 - 15 . (canceled)