Multi-chips stacked package

Abstract

A multi-chips stacked package mainly comprises a substrate, a first lower chip, a second lower chip, an upper chip and a carrier. The substrate has an upper surface, and the first lower chip and the second lower chip are disposed on the upper surface of the substrate and electrically connected to the substrate. The carrier is disposed on and electrically connected to the first lower chip and the second lower chip simultaneously, and the upper chip is mounted on the carrier. Moreover, the upper chip is electrically connected to the substrate through the carrier, the first lower chip or the second lower chip.

1 - 20 . (canceled)  
   
   
       21 . A multi-chips stacked package, comprising: 
 a substrate having an upper surface and a lower surface;    a first lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;    a second lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;    a carrier disposed on the first lower chip and the second lower chip simultaneously; and    an upper chip disposed on the carrier and electrically connected to the carrier,    wherein the carrier comprises a circuit layer respectively electrically connected to the first lower chip and the second lower chip through at least one electrically conductive wire, and the first lower chip and the second lower chip are respectively electrically connected to the substrate through at least one electrically conductive wire.    
   
   
       22 . The multi-chips stacked package of  claim 21 , wherein the upper chip is electrically connected to the circuit layer of the carrier through a plurality of electrically conductive wires.  
   
   
       23 . The multi-chips stacked package of  claim 21 , wherein the upper chip is electrically connected to the circuit layer of the carrier through a plurality of electrically conductive bumps.  
   
   
       24 . The multi-chips stacked package of  claim 21 , wherein the first lower chip apart from the second lower chip with a distance.  
   
   
       25 . The multi-chips stacked package of  claim 24 , wherein the distance is smaller than the length of the carrier.  
   
   
       26 . The multi-chips stacked package of  claim 21 , wherein the substrate and/or the carrier is a printed circuit board.  
   
   
       27 . The multi-chips stacked package of  claim 21 , further comprising a plurality of solder balls formed on the lower surface of the substrate.  
   
   
       28 . A multi-chips stacked package, comprising: 
 a substrate having an upper surface and a lower surface;    a first lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;    a second lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;    a carrier disposed on the first lower chip and the second lower chip simultaneously; and    an upper chip disposed on the carrier and electrically connected to the carrier,    wherein the carrier comprises a circuit layer electrically connected to the substrate through at least one electrically conductive wire, and the first lower chip and the second lower chip are respectively electrically connected to the substrate through at least one electrically conductive wire.    
   
   
       29 . The multi-chips stacked package of  claim 28 , wherein the upper chip is electrically connected to the circuit layer of the carrier through a plurality of electrically conductive wires.  
   
   
       30 . The multi-chips stacked package of  claim 28 , wherein the upper chip is electrically connected to the circuit layer of the carrier through a plurality of electrically conductive bumps.  
   
   
       31 . The multi-chips stacked package of  claim 28 , wherein the first lower chip is apart from the second lower chip with a distance.  
   
   
       32 . The multi-chips stacked package of  claim 31 , wherein the distance is smaller than the length of the carrier.  
   
   
       33 . The multi-chips stacked package of  claim 28 , wherein the substrate and/or the carrier is a printed circuit board.  
   
   
       34 . The multi-chips stacked package of  claim 28 , further comprising a plurality of solder balls formed on the lower surface of the substrate.  
   
   
       35 . A multi-chips stacked package, comprising: 
 a substrate having an upper surface and a lower surface;    a first lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;    a second lower chip disposed on the upper surface of the substrate and electrically connected to the substrate;    a carrier disposed on the first lower chip and the second lower chip simultaneously; and    an upper chip disposed on the carrier and electrically connected to the carrier;    wherein the carrier comprises a core layer and a circuit layer, the upper chip is electrically connected to the circuit layer of the carrier through a plurality of electrically conductive wires, the circuit layer of the carrier is electrically connected to the first lower chip or the second lower chip through at least one electrically conductive bump, and the first lower chip and the second lower chip are respectively electrically connected to the substrate through at least one electrically conductive wire.    
   
   
       36 . The multi-chips stacked package of  claim 35 , wherein the first lower chip and/or the second lower chip are/is electrically connected to the substrate through a plurality of electrically conductive bumps.  
   
   
       37 . The multi-chips stacked package of  claim 35 , wherein the first lower chip is apart from the second lower chip with a distance.  
   
   
       38 . The multi-chips stacked package of  claim 37 , wherein the distance is smaller than the length of the carrier.  
   
   
       39 . The multi-chips stacked package of  claim 35 , wherein the substrate and/or the carrier is a printed circuit board.  
   
   
       40 . The multi-chips stacked package of  claim 35 , further comprising a plurality of solder balls formed on the lower surface of the substrate.