Queue manager having a multi-level arbitrator

Abstract

In some embodiments an apparatus is described that includes a plurality of registers associated with a plurality of queues storing data awaiting processing. The registers track amount and location of data for the associated queues and generate a request for dequeuing the data when the associated queue has a certain amount of data associated therewith. The apparatus includes an arbitrator to arbitrate among the requests and to forward an arbitrated request for processing. Other embodiments are otherwise disclosed herein.

1 . An apparatus comprising 
 a plurality of registers associated with a plurality of queues storing data awaiting processing, wherein the registers track amount and location of data for the associated queues and generate a request for dequeuing the data when the associated queue has a certain amount of data associated therewith; and    an arbitrator to arbitrate among the requests and to forward an arbitrated request for processing.    
   
   
       2 . The apparatus of  claim 1 , wherein said arbitrator includes a plurality of arbiters, wherein the arbiters are arranged in at least two levels, wherein the arbiters in a first level receive requests from the registers, and wherein the arbiters in a second level receive requests from the first level arbiters.  
   
   
       3 . The apparatus of  claim 2 , wherein the first level arbiters include input control signals to synchronize reset of said arbitrator.  
   
   
       4 . The apparatus of  claim 3 , wherein the input control signals from the first level arbiters are provided to a logical AND gate to synchronize reset of the first level arbiters.  
   
   
       5 . The apparatus of  claim 3 , wherein an input control signal for a first level arbiter is activated when the first level arbiter has no requests for processing.  
   
   
       6 . The apparatus of  claim 5 , wherein each of the first level arbiters includes a logical AND gate to AND the input control signals from other first level arbiters, wherein the first level arbiters are reset if output of the logical AND is activated.  
   
   
       7 . The apparatus of  claim 2 , wherein the arbiters utilize a round robin arbitration scheme.  
   
   
       8 . The apparatus of  claim 2 , wherein the arbiters utilize a complex arbitration scheme that includes different weights for different inputs.  
   
   
       9 . The apparatus of  claim 2 , wherein type of arbitration used by the arbiters can be set.  
   
   
       10 . The apparatus of  claim 1 , wherein said arbitrator includes at least two priority levels, wherein a lower priority level arbitrates among requests from lower priority queues and a higher priority level arbitrates among requests from higher priority queues and the lower priority level.  
   
   
       11 . The apparatus of  claim 1 , wherein said arbitrator receives flow control credits and only forwards requests if credits are available.  
   
   
       12 . The apparatus of  claim 11 , wherein said arbitrator includes a preemptive portion, wherein requests from the preemptive portion are forwarded even if no credits are available.  
   
   
       13 . A network processor comprising 
 at least one receiver to receive data from external sources, wherein the data is stored in queues while the data awaits processing, wherein the data is assigned to a specific queue based on parameters associated with the data;    a queue manager to track status of queues and to arbitrate among requests for processing the queues, wherein said queue manager includes a plurality of arbiters arranged in at least two levels, wherein the arbiters in a first level receive requests from the queues and the arbiters in a second level receive requests from the first level arbiters, and wherein the first level arbiters include input control signals to synchronize reset thereof.    
   
   
       14 . The network processor of  claim 13 , further comprising a core processor to perform multiple operations including dequeuing the data stored in the queues based on requests from said queue manager.  
   
   
       15 . The network processor of  claim 13 , wherein the input control signals are activated when an associated first level arbiter has no requests left to process, wherein the input control signals are provided to a logical AND gate, and wherein the first level arbiters are reset if output of the logical AND gate is activated.  
   
   
       16 . The network processor of  claim 13 , wherein the arbiters are capable of utilizing simple or complex arbitration schemes based on an arbitration setting.  
   
   
       17 . The network processor of  claim 16 , wherein different levels of said queue manager use different arbitration schemes.  
   
   
       18 . The network processor of  claim 13 , wherein said queue manager includes at least two priority levels of arbitration, wherein a lower priority level arbitrates among requests from lower priority queues and a higher priority level arbitrates among requests from higher priority queues and the lower priority level.  
   
   
       19 . The network processor of  claim 13 , wherein said queue manager receives flow control credits and only forwards requests if credits are available.  
   
   
       20 . The network processor of  claim 13 , wherein said queue manager includes a preemptive portion, wherein requests from the preemptive portion are forwarded even if no credits are available.  
   
   
       21 . A system comprising 
 a network processor including    at least one receiver to receive data from external sources, wherein the data is stored in queues while the data awaits processing, wherein the data is assigned to a specific queue based on parameters associated with the data;    a queue manager to track status of queues and to arbitrate among requests for processing the queues, wherein said queue manager includes an arbitration hierarchy having arbiters arranged in at least two levels, wherein the arbiters in a first level receive requests from the queues and the arbiters in a second level receive requests from the first level arbiters, and wherein the first level arbiters include input control signals to synchronize reset thereof; and    dynamic random access memory to store data in the queues responsive to said network processor.    
   
   
       22 . The system of  claim 21 , wherein the input control signals are activated when an associated first level arbiter has no requests left to process, wherein the input control signals are provided to a logical AND gate, and wherein the first level arbiters are reset if output of the logical AND gate is activated.  
   
   
       23 . The system of  claim 21 , wherein the arbitration hierarchy includes at least two priority levels, wherein a lower priority level arbitrates among requests from lower priority queues and a higher priority level arbitrates among requests from higher priority queues and the lower priority level.  
   
   
       24 . The system of  claim 21 , wherein the arbitration hierarchy receives flow control credits and only forwards requests if credits are available.  
   
   
       25 . The system of  claim 21 , wherein said arbitrator includes a preemptive portion, wherein requests from the preemptive portion are forwarded even if no credits are available.