Semiconductor fabrication that includes surface tension control

Abstract

In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also includes vapor phase etching a layer adjacent to the side wall of the memory container with a vapor having a surface tension lowering agent.

1 . A method comprising: 
 forming an electrically insulating layer adjacent a semiconductor material;    transporting a combination of two or more agents to the electrically insulating layer, wherein at least one agent of the combination of two or more agents reduces surface tension near a surface associated with the electrically insulating layer; and    etching the surface using a different agent of the combination of two or more agents.    
   
   
       2 . The method of  claim 1 , wherein forming includes forming at least one of a doped oxide, a silicon oxide, a silicon nitride, a silicon oxynitride, and a silicate glass.  
   
   
       3 . The method of  claim 1 , wherein etching includes etching at least one of a doped oxide, a silicon oxide, a silicon nitride, a silicon oxynitride, and a silicate glass.  
   
   
       4 . The method of  claim 1 , wherein transporting includes transporting the two or more agents in a vapor phase.  
   
   
       5 . The method of  claim 1 , wherein transporting includes transporting at least one of a carboxylic and an acetic acid.  
   
   
       6 . The method of  claim 1 , wherein transporting includes transporting trifluoroacetic acid.  
   
   
       7 . The method of  claim 1 , wherein etching includes heating the combination of two or more agents.  
   
   
       8 . The method of  claim 1 , wherein etching includes wet etching.  
   
   
       9 . The method of  claim 1 , wherein transporting includes transporting an etch initiator.  
   
   
       10 . The method of  claim 1 , wherein etching includes applying ultraviolet light to the surface to provide uniform etching of the surface.  
   
   
       11 . The method of  claim 1 , wherein etching includes supplying an etch initiator in combination with the application of ultraviolet light to the surface.  
   
   
       12 . A method comprising: 
 releasing a plurality of chemical agents about a surface of an insulator;    adsorbing at least one of the plurality of chemical agents at the surface to lower surface tension; and    removing the insulator at a rate based on the lower surface tension.    
   
   
       13 . The method of  claim 12 , wherein removing includes maintaining an adsorbed layer on the surface during the removing.  
   
   
       14 . The method of  claim 12 , wherein removing includes combining an adsorbed agent with an etch product to generate an absorbed layer.  
   
   
       15 . The method of  claim 12 , wherein removing includes creating a plurality of substantially perpendicular surfaces to a surface of a semiconductor wafer.  
   
   
       16 . The method of  claim 12 , wherein absorbing includes absorbing a layer of etchant on the surface having a thickness that is greater than the thickness absent the agent lowering the surface tension.  
   
   
       17 . A method comprising: 
 combining two or more vapors, at least one of the two or more vapors for lowering cohesive forces on a surface of a material that includes silicon; and    removing the material at a specified rate based on a reduction of the cohesive forces.    
   
   
       18 . The method of  claim 17 , wherein lowering cohesive forces includes reducing capillary forces between sidewalls of neighboring container structures.  
   
   
       19 . The method of  claim 17 , wherein removing includes removing the material adjacent to a semiconductor memory element.  
   
   
       20 . The method of  claim 17 , wherein removing includes removing the material using an adsorbed layer generated from an etch product.  
   
   
       21 . The method of  claim 17 , wherein removing includes removing the material using ultraviolet light in conjunction with an etch initiator.  
   
   
       22 . The method of  claim 17 , wherein removing includes removing the material between adjacent container structures.  
   
   
       23 . The method of  claim 22 , wherein removing includes forming a sidewall associated with double-sided capacitor.  
   
   
       24 . The method of  claim 17 , wherein removing includes removing while maintaining an adsorbed layer on the surface of the material.  
   
   
       25 . A method comprising: 
 mixing a plurality of agents in a vapor phase;    reducing surface tension at a surface of an insulator using at least one of the plurality of agents; and    removing the insulator at a rate based on the surface tension.    
   
   
       26 . The method of  claim 25 , wherein removing includes removing by heating the plurality of agents at about the insulator.  
   
   
       27 . The method of  claim 25 , wherein removing includes removing using heat, ultraviolet light and an etch initiator.  
   
   
       28 . The method of  claim 25 , wherein removing includes removing using a combination of two or more of heat, ultraviolet light and an etch initiator.  
   
   
       29 . The method of  claim 25 , wherein mixing includes mixing an etch initiator.  
   
   
       30 . The method of  claim 25 , wherein mixing includes mixing a carboxylic or acetic acid.  
   
   
       31 . The method of  claim 25 , mixing includes mixing trifluoroacetic acid.  
   
   
       32 . The method of  claim 25 , wherein reducing includes reducing using at least one of trifluoroacetic acid, carboxylic and acetic acid in combination with a vapor etch product.  
   
   
       33 . The method of  claim 25 , wherein removing includes selectively removing the insulator.  
   
   
       34 . The method of  claim 25 , wherein mixing includes premixing at a specified location.  
   
   
       35 . The method of  claim 25 , wherein reducing includes maintaining an adsorption layer on the surface of the insulator during removal of the insulator.  
   
   
       36 . The method of  claim 35 , wherein maintaining includes an adsorbed layer of etchant on the surface.  
   
   
       37 . An apparatus comprising: 
 means for providing a surface tension lowering formulation;    a mixer coupled to an etch formulation source;    a vapor etch chamber coupled to receive vapor comprising an etch formulation from the mixer and to receive a surface tension lowering formulation, wherein the vapor etch chamber is configured to accept an ultraviolet light source and to permit an adsorption layer to be maintained on a surface adjacent a semiconductor wafer.    
   
   
       38 . The apparatus of  37 , wherein the mixer is coupled to the means for providing a surface tension lowering formulation.  
   
   
       39 . The apparatus of  37 , wherein the means for providing a surface tension lowering formulation is coupled directly to the vapor etch chamber.  
   
   
       40 . The apparatus of  37 , wherein the means for providing a surface tension lowering formulation is coupled to the vapor etch chamber through a valve, wherein the valve is further coupled to the mixer.  
   
   
       41 . The apparatus of  37 , wherein the vapor etch chamber is coupled to receive the surface tension lowering formulation from the mixer.  
   
   
       42 . The apparatus of  37 , wherein the surface tension lowering formulation includes at least one of a carboxylic, and acetic acid.  
   
   
       43 . The apparatus of  37 , wherein the surface tension lowering formulation includes trifluoroacetic acid.