Amplifier circuit with output delay selectively changed according to common mode voltage level, associated replica delay circuit and internal clock generator

Abstract

An amplifier circuit having an output delay that is selectively changed in accordance with a common mode voltage level. A replica delay circuit adapted for use within an internal clock generator include such an amplifier circuit. The amplifier circuit includes a first amplifier generating internal signal in response to input signals changes a common mode voltage level of the internal signals in response to control signals. The amplifier also includes a second amplifier comparing voltage levels of the internal signals, generating an output signal in accordance with a comparison result, and changing a duty cycle of the output signal when the common mode voltage level of the internal signals is changed.

1 . An amplifier circuit comprising; 
 a first amplifier, outputting internal signals in response to input signals and changing a common mode voltage level defined by the internal signals in response to control signals; and    a second amplifier, comparing voltage levels of the internal signals, outputting an output signal in accordance with a comparison result, and changing a duty cycle of the output signal in accordance with changes in the common mode voltage level of the internal signals.    
   
   
       2 . The amplifier circuit of  claim 1 , wherein the first amplifier changes a voltage of one of the internal signals in response to the control signals, thereby changing the common mode voltage level of the internal signals.  
   
   
       3 . The amplifier circuit of  claim 1 , wherein the first amplifier further comprises: 
 a differential amplifier, comprising a load circuit comparing the voltage levels of the input signals, and outputting the internal signals in accordance with a comparison result; and    a common mode control circuit connected in parallel with the load circuit and changing the common mode voltage level of the internal signals in response to the control signals.    
   
   
       4 . The amplifier circuit of  3 , wherein the load circuit further comprises a first load connected between a first node and a second node and a second load connected between the first node and a third node, and wherein the common mode control circuit further comprises: 
 a first common mode change circuit connected in parallel with the first load and changing a resistance between the first node and the second node in response to first control signals among the control signals; and    a second common mode change circuit connected in parallel with the second load and changing a resistance between the second node and the third node in response to second control signals among the control signals.    
   
   
       5 . The amplifier circuit of  4 , wherein the first common mode change circuit further comprises: 
 a plurality of first NMOS transistors having drains connected to the first node, sources connected to the second node, and gates connected respectively to the first control signals; and,    wherein the second common mode change circuit further comprises a plurality of second NMOS transistors having drains connected to the first node, sources connected to the third node, and gates connected respectively to the second control signals.    
   
   
       6 . The amplifier circuit of  5 , wherein the internal signals include a first internal signal and a second internal signal complementary to the first internal signal, and 
 wherein, upon enabling one or more of the first control signals, the one or more of the plurality of first NMOS transistors are turned on, and wherein, upon enabling one or more of the second control signals, one or more of the plurality of second NMOS transistors are turned on, such that    upon increasing the number of NMOS transistors in the plurality of first NMOS transistors turned off, a voltage level of the second internal signal correspondingly decreases, and upon increasing the number of NMOS transistors in the plurality of second NMOS transistors turned off, a voltage level of the first internal signal correspondingly decreases.    
   
   
       7 . The amplifier circuit of  claim 6 , wherein as the voltage level of the second internal signal decreases, a duty cycle of the output signal correspondingly decreases, and as the voltage level of the first internal signal decreases, the duty cycle of the output signal correspondingly increases.