Semiconductor device and method of manufacturing the semiconductor device

Abstract

In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by an isolation layer. An etching mask is formed on the active region and the isolation layer to have a silicidation prevention pattern that at least partially exposes the active region. A gate structure is formed on the exposed active region. A gate spacer is formed on a sidewall of the gate structure positioned on the silicidation prevention pattern. Source/drain regions are formed on the active region using the gate spacer as a mask to thereby form the semiconductor device. Since voids may not be generated in a transistor of the semiconductor device or intrusion of the transistor may be prevented in the silicidation process, the semiconductor device including the transistor may have improved reliability and electrical characteristics.

1 . A semiconductor device comprising: 
 a substrate including an isolation layer and an active region defined by the isolation layer;    a gate structure formed on the active region;    a silicidation prevention pattern formed on a portion of the active region adjacent to the gate structure; and    a gate spacer formed on a sidewall of the gate structure.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the isolation layer has a thickness thicker than a thickness of the active region.  
   
   
       3 . The semiconductor device of  claim 1 , further comprising a silicide layer formed on a portion of the active region adjacent to the silicidation prevention pattern.  
   
   
       4 . The semiconductor device of  claim 1 , wherein the substrate includes an SOI substrate having a lower semiconductor substrate, a buried insulation layer and an upper semiconductor layer, and the active region is formed by at least partially etching the upper semiconductor layer.  
   
   
       5 . The semiconductor device of  claim 1 , wherein the gate structure includes a gate insulation layer pattern formed on the active region and a gate conductive pattern formed on the gate insulation layer pattern.  
   
   
       6 . The semiconductor device of  claim 5 , wherein the gate structure further includes a silicide layer formed on the gate conductive pattern.  
   
   
       7 . The semiconductor device of  claim 1 , wherein the silicidation prevention pattern includes thermally deposited silicon nitride or silicon nitride deposited by a plasma process.  
   
   
       8 . The semiconductor device of  claim 1 , further comprising a silicon oxide layer pattern formed between the active region and the silicidation prevention pattern.  
   
   
       9 . The semiconductor device of  claim 1 , wherein the gate spacer includes material having an etching selectivity relative to the silicidation prevention pattern.  
   
   
       10 . The semiconductor device of  claim 1 , wherein the gate spacer has a single-layered structure including at least one of oxide, nitride and a multi-layered structure including oxide and nitride.  
   
   
       11 . The semiconductor device of  claim 1 , further comprising an offset spacer formed between the gate spacer and the sidewall of the gate structure.  
   
   
       12 . The semiconductor device of  claim 1 , wherein the active region includes source/drain regions formed thereon and source/drain extension regions formed between the gate spacer and the source/drain regions.  
   
   
       13 . The semiconductor device of  claim 1 , wherein the active region includes a recess, and the gate structure is positioned on the recess.  
   
   
       14 . The semiconductor device of  claim 13 , further comprising an additional spacer formed between the gate spacer and the sidewall of the gate structure.  
   
   
       15 . A semiconductor device comprising: 
 an SOI substrate including a lower semiconductor layer, a buried insulation layer and a three-dimensional active region having a polygonal structure formed on the buried insulation layer;    a gate structure formed on the buried insulation layer, wherein the gate structure encloses the active region;    a silicidation prevention pattern formed on a portion of the active region adjacent to the gate structure; and    a gate spacer formed on a sidewall of the gate structure.    
   
   
       16 . The semiconductor device of  claim 15 , further comprising channel regions formed on an upper portion and lateral portions of the active region.  
   
   
       17 . The semiconductor device of  claim 15 , further comprising a silicide layer formed on a portion of the active region adjacent to the silicidation prevention pattern.  
   
   
       18 . The semiconductor device of  claim 15 , wherein the active region includes a recess, and the gate structure is formed on the recess.  
   
   
       19 . The semiconductor device of  claim 18 , further comprising an additional gate spacer formed between the sidewall of the gate structure and the gate spacer.