Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process

Abstract

A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

1 . A non-volatile memory system including one or more non-volatile memory cells, each comprising: 
 a plurality of active semiconductor regions;    a floating gate electrode extending over portions of the active semiconductor regions, the floating gate electrode connecting various elements of the non-volatile memory cell; and    a patterned silicide-blocking layer located over the floating gate electrode, the patterned silicide-blocking layer fully covering and preventing silicide formation on portions of the floating gate electrode located over the active semiconductor regions.    
     
     
         2 . The non-volatile memory system of  claim 1 , wherein the patterned silicide-blocking layer exposes portions of the active semiconductor regions, wherein silicide is formed on the exposed portions of the active semiconductor regions.  
     
     
         3 . The non-volatile memory system of  claim 2 , wherein the patterned silicide-blocking layer extends over active semiconductor regions of the non-volatile memory cells.  
     
     
         4 . The non-volatile memory system of  claim 1 , wherein the patterned silicide blocking layer extends over the active semiconductor regions, thereby preventing silicide formation on the active semiconductor regions.  
     
     
         5 . The non-volatile memory system of  claim 1 , wherein the floating gate electrode is doped with p-type and n-type impurities.  
     
     
         6 . The non-volatile memory system of  claim 5 , further comprising an active isolation region, wherein the floating gate electrode includes a p-n interface located over the active isolation region.  
     
     
         7 . The non-volatile memory system of  claim 6 , wherein the patterned silicide-blocking layer exposes the p-n interface of the floating gate electrode, wherein silicide is formed on the p-n interface of the floating gate electrode.  
     
     
         8 . The non-volatile memory system of  claim 1 , wherein each of the one or more non-volatile memory cells further comprises a dielectric sidewall spacer located immediately adjacent to the floating gate electrode, wherein the patterned silicide-blocking layer extends over the dielectric sidewall spacer.  
     
     
         9 . The non-volatile memory system of  claim 8 , wherein the patterned silicide-blocking layer entirely covers the floating gate electrode and the dielectric sidewall spacer.  
     
     
         10 . The non-volatile memory system of  claim 1 , wherein the patterned silicide-blocking layer comprises a dielectric material.  
     
     
         11 . The non-volatile memory system of  claim 1 , wherein silicide regions are located on the active semiconductor regions, the silicide regions being located entirely within, and separated from, edges of the active semiconductor regions.  
     
     
         12 . The non-volatile memory system of  claim 1 , wherein the patterned silicide-blocking layer has a thickness that is substantially less than an initially deposited thickness of material used to create the patterned silicide-blocking layer.  
     
     
         13 . The non-volatile memory system of  claim 1 , wherein each of the one or more non-volatile memory cells includes an access transistor and a capacitor structure, which are connected by the floating gate electrode.  
     
     
         14 . A method of fabricating anon-volatile memory system including one or more non-volatile memory cells, each comprising: 
 forming a plurality of active regions in a semiconductor substrate;    forming a floating gate electrode over portions of the active semiconductor regions, the floating gate electrode connecting various elements of the non-volatile memory cell; and    forming a patterned silicide-blocking layer over the floating gate electrode, whereby the patterned silicide-blocking layer fully covers and prevents silicide formation on portions of the floating gate electrode located over the active semiconductor regions.    
     
     
         15 . The method of  claim 14 , wherein the step of forming the patterned silicide-blocking layer comprises exposing portions of the active semiconductor regions, the method further comprising forming silicide on the exposed portions of the active semiconductor regions.  
     
     
         16 . The method of  claim 15 , wherein the step of forming the patterned silicide-blocking layer results in the patterned silicide-blocking layer extending over active semiconductor regions of adjacent non-volatile memory cells.  
     
     
         17 . The method of  claim 14 , further comprising using the patterned silicide-blocking layer to prevent silicide formation on the active semiconductor regions.  
     
     
         18 . The method of  claim 14 , further comprising: 
 doping a first region of the floating gate electrode with p-type impurities; and    doping a second region of the floating gate electrode with n-type impurities, wherein a p-n interface is formed in the floating gate electrode.    
     
     
         19 . The method of  claim 18 , further comprising: 
 forming an active region isolation region in the semiconductor substrate; and    forming the p-n interface over the active isolation region.    
     
     
         20 . The method of  claim 19 , wherein the step of forming the patterned silicide-blocking layer comprises exposing the p-n interface of the floating gate electrode, the method further comprising forming silicide on the exposed p-n interface of the floating gate electrode.  
     
     
         21 . The method of  claim 14 , further comprising: 
 forming a dielectric sidewall spacer adjacent to the floating gate electrode; and    forming the patterned silicide-blocking layer such that the patterned silicide-blocking layer covers the dielectric sidewall spacer.    
     
     
         22 . The method of  claim 14 , further comprising forming silicide regions on the active semiconductor regions, the silicide regions being located entirely within, and separated from, edges of the active semiconductor regions.  
     
     
         23 . The method of  claim 14 , further comprising: 
 forming silicide, wherein the patterned silicide-blocking layer covers the entire non-volatile memory cell, preventing silicide formation thereon;    performing an etch which reduces the thickness of the patterned silicide-blocking layer; and then    performing a contact etch which extends through the patterned silicide-blocking layer.    
     
     
         24 . The method of  claim 23 , wherein the etch is selective to silicon, wherein the etch is performed until the silicide blocking layer is completely removed.  
     
     
         25 . The method of  claim 23 , wherein the step of performing the etch further comprising: 
 forming a mask which exposes the non-volatile memory cell system and protects other regions of the semiconductor substrate; and then    performing the etch of the silicide blocking layer through the mask.    
     
     
         26 . The method of  claim 14 , further comprising: 
 forming silicide, wherein the patterned silicide-blocking layer prevents silicide formation on portions of the floating gate electrode located over the active semiconductor regions; then    forming a pre-metal dielectric over the silicide and the patterned silicide-blocking layer;    forming a first mask over the pre-metal dielectric, wherein the first mask includes openings where contacts are to be formed through the patterned silicide-blocking layer;    performing a partial etch of the pre-metal dielectric through the openings in the first mask;    forming a second mask over the pre-metal dielectric, wherein the second mask includes openings where all contacts are to be formed; and then    performing a contact etch thorugh the openings of the second mask, wherein the contact etch extends through the patterned silicide-blocking layer.    
     
     
         27 . The method of  claim 26 , wherein the step of forming the second mask comprises depositing a hard-mask film.  
     
     
         28 . The method of  claim 26 , further comprising: 
 forming the first mask by forming a first set of openings through a photoresist layer; and    forming the second mask by subsequently forming a second set of openings through the photoresist layer.    
     
     
         29 . The method of  claim 26 , further comprising: 
 forming the first mask by forming a first set of openings through a first photoresist layer; and    forming the second mask by forming a second set of openings through a second photoresist layer.