Methods to make DRAM fully compatible with SRAM

Abstract

This invention provides practical methods to make a DRAM fully compatible with existing SRAM products. This is accomplished by design and manufacture methods according to the invention, which includes a method to reduce standby power of reference voltage generators and a method to avoid the alpha particle problem using a novel error correction code (ECC) mechanism. The reference voltage generator of the present invention can adjust the values of output voltage and driving power separately following simple procedures. It has very strong driving power to maintain the reference voltage, which is necessary to support high-speed operation of memory devices of the present invention. In the mean time, its standby power can be reduced by orders of magnitudes using simple control mechanism, which is necessary to make our memory device compatible with the properties of existing SRAM products. There is no need to use feedback circuits or operation amplifiers, so the circuit is extremely stable and reliable. It is an ideal reference voltage generator to generate the bit line pre-charge voltage for a DRAM designed to emulate an SRAM device. The unique features of the ECC protection of the present invention avoid RC delay problems in prior art ECC circuits, which is necessary to support high speed operation of our products. The alpha particle problem is no longer an issue. All the supporting circuits can use repeated layouts, which is very important for memory design. The manufacture technology for embedded IC is simplified dramatically, which allow us to have high performance logic circuits. The memory devices of the present invention are therefore compatible in every detailed feature with existing SRAM products.

1 - 24 . (canceled)  
   
   
       25 . A logic transistor supported on a substrate having an embedded memory transistor also supported on same substrate provided for connection to an error-code-correction (ECC) circuit and memory cells, wherein: 
 said logic transistor having a logic-transistor gate, a logic-transistor gate oxide disposed under said logic-transistor gate, and a logic-transistor channel disposed under said logic-transistor gate oxide;    said memory transistor having a memory-transistor gate, a memory-transistor gate oxide disposed under said memory-transistor gate, and a memory-transistor channel disposed under said memory-transistor gate oxide; and    said logic-transistor gate oxide having substantially the same thickness as said memory-transistor gate oxide, and said logic-transistor channel having substantially the same dopant concentration as said memory-transistor channel.    
   
   
       26 . The logic transistor of  claim 25  wherein: 
 said memory-transistor gate oxide and said logic-transistor gate oxide having a thickness less than or equal to one-hundred Angstroms.    
   
   
       27 . A method for manufacturing a logic transistor on a substrate with an embedded memory transistor also on said substrate ready for connection to an error-code-correction (ECC) circuit, comprising: 
 performing a channel ion implant to form a logic-transistor channel and a memory-transistor channel having substantially the same doping concentration; and    forming a gate oxide layer for said logic transistor and said memory transistor having substantially the same thickness over said logic-transistor channel and said memory-transistor channel.    
   
   
       28 . The method for manufacturing said logic transistor of  claim 27  further comprising a step of: 
 forming a gate on top of said gate oxide layer for said logic transistor and said memory transistor having substantially the same thickness.    
   
   
       29 . The method for manufacturing said logic transistor of  claim 27  wherein: 
 said step of forming said gate oxide layer for said logic transistor and said memory transistor is a step of forming said gate oxide layer with a thickness less than or equal to one-hundred Angstroms.    
   
   
       30 . The method for manufacturing said logic transistor of  claim 27  wherein: 
 said step of performing a channel ion implant to form a logic-transistor channel and a memory-transistor channel is a step of forming said logic-transistor channel and said memory-transistor channel having a channel length less than or equal to  0 . 5  micrometers.