Apparatus and method for reducing test resources in testing drams

Abstract

An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

1 . (canceled)  
   
   
       2 . A wafer probe for testing a memory device, the wafer probe comprising: 
 a plurality of conductive pins having a control pin configured to output to at least one memory device a control signal having a precharge signal defined by a first portion of the control signal and a latch signal defined by a second portion of the control signal.    
   
   
       3 . The wafer probe of  claim 2 , wherein the first portion of the control signal is a leading edge of the control signal.  
   
   
       4 . The wafer probe of  claim 3 , wherein the second portion of the control signal is a trailing edge of the control signal.  
   
   
       5 . The wafer probe of  claim 2 , wherein the at least one memory device comprises a dynamic random access memory (DRAM).  
   
   
       6 . The wafer probe of  claim 2 , wherein the plurality of conductive pins is configured to positionally align with bonding pads of at least three memory devices to be tested.  
   
   
       7 . The wafer probe of  claim 2 , further comprising compare circuitry configured to compare data read from the at least one memory device with test data in order to test the integrity of the at least one memory device.  
   
   
       8 . Control circuitry for use with a wafer probe in testing a computer memory device, the control circuitry comprising: 
 a first input configured to receive from a control pin of a wafer probe a control signal having a precharge signal defined by a first portion of the control signal and a latch signal defined by a second portion of the control signal.    
   
   
       9 . The control circuitry of  claim 8 , further comprising a compression module configured to receive, from the wafer probe, data to be written to multiple locations on a computer memory device.  
   
   
       10 . The control circuitry of  claim 9 , wherein the compression module is configured to replicate a single data bit to the multiple memory locations during a write operation.  
   
   
       11 . The control circuitry of  claim 10 , wherein the compression module is configured to output a failure signal when data bits read from the multiple memory locations have different values.  
   
   
       12 . The control circuitry of  claim 8 , further comprising a second input configured to receive from the wafer probe a testing signal for indicating whether a testing operation by the wafer probe is a read operation or a write operation.  
   
   
       13 . The control circuitry of  claim 12 , further comprising a third input configured to receive from the wafer probe a bank address, a row address and a column address for activating a memory location.  
   
   
       14 . A device for testing a computer memory device, the testing device comprising; 
 clock circuitry configured to output a control signal having a precharge signal defined by a first portion of the control signal and a latch signal defined by a second portion of the control signal; and    a plurality of conductive pins, the plurality of conductive pins having a control pin coupled to the clock circuitry and configured to output the control signal to at least one memory device.    
   
   
       15 . The testing device of  claim 14 , wherein the plurality of conductive pins comprises one hundred pins.  
   
   
       16 . The testing device of  claim 14 , further comprising function circuitry configured to output a second signal for selecting whether a testing function by the testing device is a read testing function or a write testing function.  
   
   
       17 . The testing device of  claim 14 , wherein the plurality of conductive pins is configured to concurrently align with bonding pads of at least three memory devices.  
   
   
       18 . The testing device of  claim 17 , further comprising read circuitry configured to read data from each of the at least three memory devices.  
   
   
       19 . The testing device of  claim 17 , wherein the plurality of conductive pins comprises at most nine address pins for each of the at least three memory devices, wherein the address pins are configured to output address bits to each of the at least three memory devices.  
   
   
       20 . The testing device of  claim 17 , further comprising compare circuitry configured to compare data read from each of the at least three memory devices with test data in order to test the integrity of each of the at least three memory devices.  
   
   
       21 . The testing device of  claim 14 , wherein the first portion of the control signal is a leading edge of the control signal and the second portion of the control signal is a trailing edge of the control signal.